Graduate Engineer, System IP Engineering
Posted Updated
Description
- System IP microarchitecture specification and design
- SystemVerilog RTL verification and debug
- Formal bring-up of non-trivial IP blocks to achieve required quality levels
- Collaboration with engineers across design, performance modelling, validation, and implementation to meet functional requirements, performance, power and area goals
- Bachelor or Masters degree in Electrical Engineering or Computer Engineering by the programme start date
- Experience of block level RTL design and verification for non-trivial ASIC or FPGA developments
- SystemVerilog knowledge
- Familiarity with the Arm AMBA specifications or other bus protocols
- Understanding of digital design including CPU, GPU and cache concepts, memory, I/O
- Scripting skills with Perl, Python or similar
- Starting salary of HUF 10,950,000 per annum
- Comprehensive rewards package
- Clear opportunities to progress within the salary range at Arm
- Mid-year and year-end reviews with two formal progression windows each year
- Access to Grad-teach-Grads workshops, guest speaker series, and social events
- Opportunity to join the Graduate Committee for planning, networking, and coordination skills development
- Invitation to the Global Graduate Conference (GGC)
- Relocation support for domestic and regional moves within Europe
- Visa sponsorship support