Intern, System IP Engineering
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- SystemVerilog RTL verification and debug for System IP components
- Formal bring-up of non-trivial IP blocks to achieve required quality levels
- Collaboration with engineers across design, performance modelling, validation, and implementation to meet functional requirements, performance, power and area goals
- Enrollment in a Master's or Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
- Experience of block level RTL design and verification for non-trivial ASIC or FPGA developments
- SystemVerilog knowledge
- Familiarity with Arm AMBA specifications or other bus protocols
- Understanding of digital design including CPU, GPU and cache concepts, memory, I/O
- Scripting skills with Perl or Python
- Experience of block level RTL design and verification for non-trivial ASIC or FPGA developments with SystemVerilog preferred
- Familiarity with the Arm AMBA specifications or other bus protocols
- Understanding of digital design including CPU, GPU and cache concepts, memory, I/O
- Scripting skills with Perl, Python or similar
- Internship duration of approximately 6 months starting in 2027
- Regular feedback and development opportunities
- Social activities to connect with peers
- End of internship celebration
- Opportunity to be considered for future Graduate positions subject to performance
- Competitive salary of HUF 5,250,000 per annum
- On-the-job learning and mentoring/buddy schemes
- Hybrid working environment
- Health and wellness support including quarterly Day of Care
- Financial rewards beyond competitive salary
- Professional and personal development support
- Supportive community environment