IP / SoC RTL Senior / Lead Design Engineer

Our Client SeviTech is looking for IP / SoC RTL Senior / Lead Design Engineer

About our Client: http://sevitechsystems.com/

Job Designation: IP / SoC RTL Senior / Lead Design Engineer

Job Location: Bangalore

Job Type: Permanent

IP / SoC RTL Senior / Lead Design Engineer

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

• Prepare block/sub-system level timing constraints.

• Integrate IP/sub-system.

• Perform basic verification either in IP Verification environment or FPGA.

Desired Skills and Experience:

• B. Tech. or M. Tech. with 6 to 8 years of experience.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Expertise in Verilog is a must.

• Should have knowledge of AMBA protocols - AXI, AHB, APB.

• Experience in Synthesis / Understanding of timing concepts for ASIC is required.

• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

• Hands on experience in Multi Clock designs, Asynchronous interface are a must.

• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus.

This is an Immediate Opportunity candidate with less than one month notice will be

preferred.

Please ignore this mail if the above profile doesn’t match with your current Job Role.

Thank you for your Valuable Time

Hoping for a Prompt Response!!!

MTec / Btec