PCIe Design Verification Engineer
NewBe an early applicantWe are looking for an enthusiastic PCIe Design Verification Engineer with 7–8 years of proven professional experience to join our IP Design team.
As a PCIe Design Verification Engineer, you will be part of a highly competent team working on high-performance IP and ASIC designs. You will create scalable UVM verification solutions and apply deep PCIe protocol expertise to ensure functional correctness, quality, and coverage closure.
Your Main Responsibilities
- Architect, develop, and maintain SystemVerilog/UVM verification environments, testbenches, and test cases.
- Verify PCIe IP functionality, protocol compliance, and interoperability across relevant configurations.
- Plan and execute regressions; analyze failures and work closely with design, architecture, and integration teams on debug and resolution.
- Define, implement, and monitor code and functional coverage, driving closure to verification-plan objectives.
- Communicate verification status, risks, issues, and results clearly at project checkpoints.
Requirements
- 7–8 years of relevant ASIC/IP design verification experience.
- Strong understanding of ASIC design verification methodologies and principles.
- Proficiency in SystemVerilog and UVM.
- Strong PCIe protocol knowledge.
- Demonstrated experience in testbench and testcase development, regression execution and validation, and code and functional coverage.
- Preferred: proficiency in Perl and/or Python scripting.
- Preferred: experience working with foundry data from TSMC, Intel, and/or Samsung