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Principle VLSI/ ASIC Design Engineer

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Summary

Principal-level engineer at HPE leading ASIC/VLSI architecture and RTL design for complex networking and compute SoCs — from early architecture exploration and microarchitecture through RTL, synthesis, timing closure, and production readiness. Core stack: Verilog/SystemVerilog RTL, ASIC design flows, low-power design, DFT, and high-speed interfaces.

  • The Principle VLSI/ASIC Design Engineer is responsible for the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions
  • This role contributes to early-stage architecture and design exploration and carries concepts through detailed design implementation for networking, compute, and other complex SoC applications
  • The engineer will serve as a recognized technical authority in ASIC and VLSI design, influencing product strategy, technology roadmaps, architectural direction, and implementation methodologies across organizations and business units
  • Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications
  • Define architectural approaches, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps
  • Design, develop, and modify complex RTL blocks using industry-standard hardware description languages and design practices
  • Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness
  • Analyze design tradeoffs involving performance, power, area, scalability, reliability, and time to market
  • Develop and evaluate VLSI components and hardware systems across multiple platforms and product organizations
  • Conduct design reviews and evaluate product designs for compliance with architecture, implementation guidelines, quality standards, and industry best practices
  • Establish operating data and performance expectations through analytical modeling, simulation, prototyping, and experimental evaluation
  • Provide tangible, data-driven feedback to improve product quality, reduce design risk, and mitigate potential product failures
  • Contribute to organization-wide ASIC design architectures, methodologies, and standards
  • Create integration plans for incorporating new technologies, IP, design practices, and implementation improvements into existing architectures
  • Identify emerging technologies, innovations, tools, and external partnerships that support business objectives and technology roadmaps
  • Review material specifications, hardware designs, electrical component requirements, and related technical documentation
  • Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, and external development teams
  • Influence technical decisions made by business leadership, development partners, suppliers, and industry standards organizations
  • Provide technical leadership for significant projects and programs, connecting teams across functions around common objectives
  • Mentor less-experienced engineers and promote design innovation, engineering excellence, and knowledge sharing
  • Serve as an internal authority on ASIC and VLSI engineering, providing consultation across organizations and business units

Benefits

  • Recognition for your contributions, and potential participation in long-term incentives like annual equity awards
  • Subsidized health insurance, retirement programs and paid time off, including an industry-leading maternity and paternity leave package
  • A hybrid, flexible work model that ensures connectivity, a commitment to our culture and continued impact for team members
  • The chance to earn an annual bonus based on performance
  • Opportunities for personal and professional development to help you reach your career goals
  • The role requires strong technical leadership, innovation, cross-functional collaboration, and the ability to mentor engineers while delivering high-quality, scalable, and production-ready designs
  • Demonstrated experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications
  • Experience leading architecture and design exploration through RTL implementation and product integration
  • Design verification experience is not required but is highly desirable
  • Typically, 9 + or more years of experience in ASIC, VLSI, SoC, or related hardware design
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered
  • Proven ability to influence decisions across business units, functions, senior leadership, external partners, and industry organizations
  • Is recognized as an internal authority in key ASIC, RTL, and VLSI technology areas
  • Understanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff
  • Strong collaboration skills and experience working effectively across geographically distributed, cross-functional teams
  • Provides technical leadership for major projects and programs and unites teams around common goals
  • Ability to mentor engineers and provide technical direction without direct management responsibility
  • Ability to evaluate design alternatives and make recommendations based on performance, power, area, cost, risk, and schedule
  • Strong written and verbal communication skills, with the ability to explain complex technical concepts to both technical and executive audiences
  • Demonstrated innovation, including the development or adoption of new technologies, methodologies, or design practices
  • Strong analytical, problem-solving, and technical decision-making skills
  • Ability to communicate architectural proposals, design plans, tradeoffs, risks, and results effectively
  • Actively mentors engineers and contributes to the broader technical community
  • Delivers unique, long-lasting improvements in areas such as time to market, product quality, cost reduction, scalability, and customer value
  • Makes substantial technical contributions to significant HPE products, programs, or strategic architectural initiatives
  • Experience with design modeling, simulation, performance analysis, and empirical evaluation methodologies
  • Proven experience developing complex RTL using Verilog, System Verilog, or comparable hardware description languages
  • Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development
  • Experience defining and improving design methodologies, tools, automation, and engineering practices
  • Acts as a go-to creator and innovator for critical business and technology challenges
  • Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures
  • Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths
  • Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning
  • Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies
  • Knowledge of industry standards and leading-edge ASIC implementation technologies
  • Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers

Skills

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