軟體研發類 (18526): Applications Engineering, Sr Staff Engineer (VC Formal)

請上傳英文履歷至官網(職缺代碼18526):
https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer/44408/100063255136

You Are:
You are a passionate engineer with a keen interest in the intricate world of formal verification and EDA tool validation. You thrive on solving complex technical problems and are motivated by the challenge of ensuring the highest standards for cutting-edge verification solutions. With a strong background in digital design and formal methods, you are well-versed in scripting and comfortable in Unix/Linux environments. You bring a collaborative spirit, excellent analytical abilities, and a commitment to continuous learning and improvement.

You thrive in dynamic, fast-paced settings, where collaboration and innovation are at the forefront. Your expertise spans across protocols like APB, AHB, AXI, ACE, CHI, I2C, SPI and IP like RISC-V. You are also aware of other protocols like DDR, CXL, PCIe, AMBA, Ethernet, USB, and MIPI, and you are well-versed in Formal Verification tools like VC Formal and methodologies. You are not only proficient in SystemVerilog but you also leverage scripting and programming languages (TCL, Perl, Python) to drive productivity and efficiency. Your commitment to quality is unwavering, and you have a keen eye for detail, ensuring coverage-driven verification processes and assertion-based checks are meticulously implemented.

What You’ll Be Doing:
Develop/maintain Assertion IP for complex bus protocols (AMBA family, Memory interfaces like DDR etc.)
Develop differentiating features and innovative methodologies for formal verification tools
Validate advanced features of EDA tools such as Synopsys VC Formal, including Property Verification (FPV), Sequential Equivalence (SEQ), Connectivity Checking and other Apps.
Collaborate closely with cross-functional teams, including R&D, application engineers, and product management, to define and enhance tool features
Stay current with the latest formal verification methodologies, industry standards, and emerging trends to drive innovation in tool development.
The Impact You Will Have:

What You’ll Need:
1.Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related discipline.
2.2–14 years of experience in formal verification or EDA tool validation.
3.Hands-on experience with formal verification tools such as Synopsys VC Formal
4.Proficient in developing synthesizable code for development of assertion IPs like APB, AHB, AXI, ACE, CHI, I2C and SPI protocols. Knowledge of DDR, CXL, PCIe, Ethernet, USB is a bonus.
5.Proficient in writing/understanding of System Verilog Assertions (SVA)
6.Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments.

Who You Are:
Analytical problem-solver with strong debugging skills and attention to detail.
Effective communicator, able to convey technical concepts clearly across teams.
Collaborative team player with a proactive approach to sharing insights and feedback.
Adaptable and eager to learn new technologies and methodologies.
Driven by curiosity, innovation, and a commitment to excellence.

The Team You’ll Be A Part Of:
You will join a dynamic and diverse engineering team focused on developing and validating world-class formal verification solutions. The team thrives on innovation, collaboration, and technical rigor, working closely with R&D, product management, and application engineers to deliver impactful products. You’ll be part of a supportive environment that values continuous learning, open communication, and the pursuit of excellence in every aspect of tool development.