Senior ASIC Frontend Engineer - RTL & SystemVerilog

Upscale AI, Inc. is seeking a seasoned ASIC Design engineer to define micro-architecture for next-generation designs and own RTL entry that meets power, performance, and area targets.

You will collaborate with architecture, verification, emulation, and physical design teams to validate test plans, closures, and DFT integration in a fast-paced startup environment. Ideal candidates have SystemVerilog expertise, 3+ years of ASIC logic design, and strong teamwork capabilities to help drive