Senior Design Engineer CAD and Methodology

Architect and optimize EDA design environments for ASIC development, own digital and analog implementation flows, configure Cadence tools, refine physical design methodologies, automate workflows with scripting and programming, troubleshoot tool and license issues, and align design constraints with cryptographic mining efficiency.

Responsibilities

• Own, develop, and maintain digital and analog EDA implementation flows.
• Configure Cadence ADE and digital implementation tools to improve productivity and silicon performance.
• Drive physical design flows covering floorplanning, placement, routing, and timing closure.
• Create and maintain automation scripts and internal tools.
• Troubleshoot tool anomalies, license constraints, and flow failures with analog and digital designers.
• Apply Bitcoin ecosystem knowledge to design constraints and flow priorities.

Requirements

• Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Hands-on integrated circuit design industry experience.
• Deep understanding of Cadence ADE architecture, environment customization, and tool capabilities.
• Production-level familiarity with Cadence Innovus or OpenROAD physical design flows.
• Fluency in TCL, Python, BASH, C, or C++.
• Understanding of the Bitcoin mining ecosystem, cryptographic hashing constraints, and ASIC-boost optimization.
• Methodology-driven approach to debugging software-hardware interactions and optimizing compute pipelines.