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佳易科技股份有限公司

Senior Digital Design Engineer

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Description

●About the Role
As a Senior Digital Design Engineer, you will play a key role in driving digital design activities across company products, design service projects, and internal IP development.
You will be responsible for RTL design, architectural reviews, functional verification, and supporting SoC integration efforts. This role suits an engineer with strong ownership, deep SoC design expertise, and solid hands-on experience in Verilog and FPGA prototyping.

●Why Join Us
A platform to grow into a technical leader in digital front-end and SoC design

●Key Responsibilities
-Perform RTL design and develop test benches for digital IP and SoC modules
-Design and integrate IP cores including CPU cores, digital controllers, and peripheral interfaces
-Conduct architecture reviews, RTL coding, functional verification, and post-synthesis simulation
-Integrate ARM CPUs into SoC platforms
-Integrate SDRAM memory controllers and support related timing/verification
-Develop and optimize interconnect systems, including:
AHB bus arbitration
Multi-layer AHB architectures
Interconnect matrix design
Design SoC peripheral IP such as GPIO, RTC, UART, I2C, I2S, SPI
-Perform RTL simulation and debugging using Verilog
-Conduct FPGA prototyping, bring‑up, and emulation
-Execute system-level validation and verification
-Support characterization and handle lab test equipment for debug
-Perform digital front-end design, simulation, and synthesis
-Run verification using System Verilog OVM methodology
-Apply low-power synthesis techniques
-Provide digital-side support for DFT and ATPG
-Develop scripts in Perl, Python, TCL, and work in UNIX/Linux environments

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