Senior Lead FPGA Verification Engineer - Actuation Systems M/F
Description
General information
Entity
Safran is an international high-technology group operating in the fields of aerospace (propulsion, equipment and interiors), space and defense. Its mission is to contribute sustainably to a safer world, where air transport becomes ever more environmentally friendly, comfortable and accessible. Present on every continent, the Group employs 110,000 people and generated €31.3 billion in revenue in 2025. Safran holds, either independently or through partnerships, leading global or European positions in its markets.Safran was ranked second in the Aerospace & Defense sector in TIME magazine's ""World's Best Companies 2025"" ranking.
Safran Electronics & Defense is an international company with more than 19,000 employees who bring together expertise and team spirit to design high-technology solutions for the aerospace, defense and space sectors. By combining human and technological intelligence, the company develops products and services for both civil and military customers, operating on land, at sea, in the air and in space.
Reference
2026-171190Position description
Domain
Research, design and development
Job field / Job profile
Electronics and automation - FPGA
Job title
Senior Lead FPGA Verification Engineer - Actuation Systems M/F
Employment type
Permanent
Part time / Full time
Full-time
Job description
Description of the Role:
In this role as a Senior Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards Requirement-Based Testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.
Primary Responsibilities:
1.Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals.
2.Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage.
3.Participate in requirement validation and requirement review.
4.Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing.
5.Actively participate in a team environment and work independently with design teams to develop verification architecture, applications, comprehensive test plans and address issues.
6.Verification environment development from scratch for block level and system level.
7.Work closely with design team on design de-bugging, coverage gap analysis etc.
8.Independently work towards functional and structural coverage closure for module and system level designs.
9.Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.
10.Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
11.Technical guidance to the junior engineers on verification tasks.
Candidate skills & requirements
Qualifications:
•Bachelor's/Master's degree in Engineering (ECE or VLSI)
•7-11 years of Industry experience with experience in development, integration & verification of ASIC/FPGA.
•Hands on experience in developing SV-UVM verification environment from scratch.
•Hands on experience with Questa or Modelsim or similar advanced simulation tools.
•Hands on experience in DO-254 verification process.
•Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently.
•Exposure to test plan generation, test bench writing, simulation of designs.
•Experience in RTL Design using VHDL, Complete FPGA development flow and FPGA verification using VHDL will be a plus.
•Experience in DOORS/Jama will be a plus.Guide Junior engineers in the project execution and take the ownership of the deliverables.
•Experience in leading team and reporting progress metrics.
•Excellent oral and written communication skills
Position location
Job location
Asia, India
City (-ies)
Candidate criteria
Minimum education level achieved
Bachelor's Degree
Minimum experience level required
More than 8 years