Senior Program Manager (資深專案經理)

✅About the job
We are seeking a Senior Program Manager to own end-to-end program execution across our LPU silicon, IP licensing deliverables, and hardware platforms. You will lead SoC programs from definition through tape-out, post-silicon validation, and production ramp, while aligning silicon, software toolchain, and hardware milestones with customer commitments. In addition to driving programs directly, you will mentor
and guide Project Managers and help establish the program management practices the company needs as it scales.

✅Key Responsibilities
●Program Planning & Execution

• Own the full program lifecycle of LPU SoC development, from definition through tape-out, post silicon validation, and production ramp.
• Build and maintain master schedules, critical paths, and resource plans across Design, Verification, DFT, Physical Design, CAD, Validation, Hardware, and Software workstreams.
• Manage program budgets, including NRE, mask/MPW costs, and vendor contracts; collaborate with design service partners and manage their progress.
• Manage change requests and assess their impact on program scope, schedule, and resources.

●Product & Customer Delivery

• Plan and track delivery schedules for IP licensing deliverables (e.g., design data packages,integration documentation, reference designs) in line with customer agreements.
• Drive Evaluation Board (EVB) and Development Board (DVB) programs from design through production and shipment, monitoring board design, power, thermal, firmware, and system integration.
• Align silicon, software toolchain (compiler, runtime, firmware), and hardware release versions to ensure consistent customer deliveries.

●Cross-Functional & External Collaboration

• Serve as the primary program interface with external partners, including foundries, IP vendors, design service companies, and OSAT providers.
• Integrate Signal Integrity (SI), Power Integrity (PI), BGA package design, and board schedules into the master program plan, ensuring design for manufacturability (DFM) and system-level performance targets are met.

●Risk Management & Process Governance

• Identify program-level risks early and develop mitigation and contingency plans.

Establish and run phase-gate reviews, tape-out sign-off checklists, and post-silicon issue tracking processes.

• Provide regular, data-driven program status reports to stakeholders, including executive leadership.

✅Qualifications (Must Have)
●8+ years of SoC/ASIC program or project management experience in the semiconductor industry.
●Led at least two tape-outs as the primary program or project manager, and at least one post silicon bring-up.
●Solid understanding of the deliverables, dependencies, and typical schedule risks at each stage of the SoC development flow, including but not limited to:

• Architecture definition and specification
• RTL design and functional verification
• Logic synthesis and Static Timing Analysis (STA)
• Physical design
• Design for Test (DFT)
• IP integration and verification
• Tape-out procedure
• Post-silicon validation
• Experience with New Product Introduction (NPI) and production ramp, working directly with foundries and OSAT providers.
• Experience managing programs involving external IP vendors or design service partners.

✅Preferred Qualifications (Nice to Have)
●Experience with IP licensing or ASIC design service programs, including customer-facing deliverables.
●Direct experience managing programs with significant SI/PI, BGA package design, and board integration challenges.
●Experience with high-speed interfaces such as PCIe, UCIe, LPDDR4/4x, LPDDR5/5x, LPDDR6, and PAM4 SerDes.
●Familiarity with multi-die / chiplet integration.
●NPI experience with accelerator cards or server products.
●Exposure to AI accelerator development (LPU, NPU, or GPU), especially for LLM workloads.
●PMP or equivalent project management certification is a plus.