Senior/Staff Engineer, Technical Manager (Design Verification)

Develop and review test plans
Develop verification environment/testbench in Module/IP/SOC level
Develop verification IP and reference model
Implement test with randomization based coverage driven verification methodology
Implement functional and functional/code coverage closure
Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC:
Low Power verification
Formal verification

#LI-WC1

Bachelor's/Master's Degree in EEE/Computer/IC design
4-10 years verification experiences
IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU
Strong experience and debugging ability on SystemVerilog/UVM
Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow
Experience on Low Power and formal verification is a plus
Strong in UNIX scripting with Pyhon, Perl, makefile Cshell
Quick to learn new technology
Singaporeans and Singapore Permanent Residents are preferred.