Senior Staff / Staff / Senior Engineer - SOC Physical Design / Backend Engineer
NOORTECH MALAYSIA SDN BHD Senior Staff / Staff / Senior Engineer - SOC Physical Design / Backend Engineer
Summary
SoC physical design (backend) engineer in Malaysia owning module-level implementation — floorplanning, P&R, clock-tree synthesis, timing closure and physical verification — for SoCs targeting automotive, robotics and HPC, plus tape-out support. Core tools: Innovus/ICC2, PrimeTime, Calibre/ICV, Tcl/Python.
Location (on-site): Malaysia (Selangor/Penang)
About the role
We are seeking an experienced SOC (System-On-Chip) Physical Design / Backend Engineer to support advanced SoC (System-On-Chip) physical implementation and tape-out activities for automotive, robotics and high-performance computing applications.
Key responsibilities
Own module-level physical implementation for SoC blocks including ARM CPU and CMN interconnect, covering floor planning, placement and routing, clock-tree synthesis, timing closure and physical verification.
Implement low-power design requirements and optimize timing, power and area (PPA).
Develop, maintain and improve backend implementation flows and technical documentation.
Work with front-end design and DFT engineers on ECO implementation and resolution of timing and logic issues.
Support chip tape-out and post-tape-out yield improvement activities.
Coordinate with external design service providers on technical interfaces, delivery standards and issue tracking.
About you
Bachelor's degree or above in Microelectronics, Electrical/Electronic Engineering or a related discipline, with 10+ years of Senior Staff SOC backend experience / 7-10 years of Staff Engineer / 4-7+ years of Senior Engineer.
Proficient in mainstream P&R tools such as Innovus / ICC2; familiar with PrimeTime STA and Calibre / ICV physical verification; basic knowledge of Design Compiler (DC).
Good understanding of low-power design flows, timing analysis and technical issue diagnosis.
Proficient in Tcl / Python; automation-flow development experience is preferred.
Experience using AI agents for backend development is an advantage.
Strong teamwork and learning ability.
7nm or advanced-node tape-out experience is preferred; TSMC N5A experience is a strong advantage.
Experience working with design service providers and aligning technical interfaces, delivery standards and issue tracking.