Silicon Physical Design Engineer
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Summary
A physical design engineer role on Google's custom silicon team in Bengaluru, owning synthesis-to-GDS implementation of complex physical partitions and optimizing power, performance, and area. Day-to-day work spans floorplanning, place and route, clock/power planning, timing and EM/IR sign-off, collaborating with RTL/DFT/CAD and ML teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.
As a Physical Design Engineer, you will contribute to improving Design Power, Performance, and Area (PPA) using various techniques. You will use your experience of physical design and machine learning to solve hard technical problems, collaborate with Register-Transfer Level/Design Verification/Design for Testability (RTL/DV/DFT) teams, and improve on Power, Performance, Area and Schedule. You will directly impact logic design and optimizations, floorplan, place and route, clock and power planning, timing analysis, Power Distribution Network (PDN) analysis and beyond. You will collaborate across Alphabet working with design, CAD and machine learning teams.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.
As a Physical Design Engineer, you will contribute to improving Design Power, Performance, and Area (PPA) using various techniques. You will use your experience of physical design and machine learning to solve hard technical problems, collaborate with Register-Transfer Level/Design Verification/Design for Testability (RTL/DV/DFT) teams, and improve on Power, Performance, Area and Schedule. You will directly impact logic design and optimizations, floorplan, place and route, clock and power planning, timing analysis, Power Distribution Network (PDN) analysis and beyond. You will collaborate across Alphabet working with design, CAD and machine learning teams.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
- Take end-to-end ownership of synthesis-to-Graphic Data System (GDS) implementation of complex physical partitions/subsystems.
- Collaborate with sign-off teams and own the convergence of Electromigration (EM)/IR, power, timing and physical verification.
- Collaborate with cross-functional teams RTL, DFT, CAD to improve Power/Performance/Area in physical design.
- Use and improve CAD recipes for PPA benefits.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience in physical design.
- Experience in high performance synthesis, Place and Route (PnR) and sign-off optimizations. Experience in sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
- Experience with programming in TCL/Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with constraints, synthesis or Clock Tree Synthesis (CTS).
- Experience using Machine Learning (ML) in physical design/signoff convergence (e.g., STA/EMIR closure).
- Knowledge of Verilog/SystemVerilog.
- Understanding of circuit design, device physics and deep submicron technology.