SOC 數位IC設計工程師(竹南/竹北)

1. SoC integration, bus fabric/high speed peripherals connection with superior quality, performance at best power and cost efficiency.
2. SoC clock, reset, power flow(UPF), ATE(scan/MBIST/analog macro test)plan and RTL design.
3. SoC design quality check and front-end design flow, such as ncverilog, verdi, Lint/CDC/LEC, power analysis, FPGA flow.
4. Built up block/SoC-level verification environment using SystemVerilog/UVM, and simulation patterns generation.