[新竹]SOC RF Physical Design Engineer

We are seeking a highly motivated and skilled Physical Design Engineer to join our team and contribute to the development of cutting-edge digital designs. In this role, you will be responsible for the physical design of complex blocks, including floor-planning, placement, clock tree synthesis, routing, timing closure, and power optimization. You will work closely with a team of talented engineers to deliver high-quality and performance-driven designs.

Responsibilities：

Perform full-chip and block-level physical design tasks, including:

• Floor-planning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Power Optimization
• Signal Integrity Analysis
• Physical Verification (DRC, LVS, ERC)
• Utilize advanced physical design methodologies and tools, with a strong focus on Synopsys ICC2 and Fusion Compiler.
• Collaborate effectively with cross-functional teams, including RTL design, verification, and analog design.
• Analyze and debug complex design issues.
• Contribute to the continuous improvement of design methodologies and flows.
• Stay abreast of the latest advancements in physical design technologies and tools.

Qualifications：

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• Minimum of 5 years of relevant experience in physical design.
• Strong hands-on experience with Synopsys ICC2 and Fusion Compiler is essential.
• Proficiency in scripting languages (e.g., TCL, Python) for automation.
• Excellent understanding of VLSI design fundamentals, including timing analysis, power analysis, and signal integrity.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork skills.
• Ability to work independently and as part of a team.