[新竹]SOC RF Physical Implementation Engineer

Our team specializes in developing and implementing cutting-edge Samsung modem and connectivity chips, which are integral components of the latest smartphone technologies. Operating at very high frequencies and utilizing the most advanced technologies available, our designs are tailored to meet the demanding requirements of Samsung phones. With a focus on in-house design development, we pride ourselves on delivering innovative solutions that drive the evolution of mobile connectivity.

Candidate will play a crucial role in providing a comprehensive RTL to GDS solution for Samsung modem and connectivity projects. This role offers a unique chance to immerse yourself in the full ASIC flow, providing invaluable experience and growth opportunities.
We are seeking individuals who are passionate, dedicated and eager to contribute to cutting edge projects.

Responsibilities：

• Timing closure for block and chip level design for multiple projects.
• Interact with design team, DFT and physical design team to close the timing of design.
• Write scripts to improve the STA methodology
• Work on Synthesis and formality flow for multiple designs

Qualifications：

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design concepts, including synthesis, timing analysis, and formal verification.
• Expert in Synopsys timing analysis tool Primetime.
• Experience in timing ecos using Synopsys and other tools.
• Familiarity with scripting languages like TCL, Perl, or Python for automation tasks.
• Knowledge of ASIC design flow, including front-end and back-end processes.
• Ability to collaborate effectively in a team environment and communicate complex technical concepts clearly.
• Strong problem-solving skills and attention to detail.
• Understanding of semiconductor fabrication processes and how they influence IC design.
• Knowledge of analog and mixed-signal design principles is beneficial for certain roles.
• Willingness to stay updated on the latest advancements in semiconductor technology and design methodologies.