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Step into an exciting, mission-led career as a Principal FPGA Engineer, shaping secure firmware that powers high-assurance defence and cyber capabilities. If you enjoy leading complex technical work, mentoring others,…
Job Description: Senior Principal Power Electronics Engineer Position Summary We are seeking a Senior Principal Power Electronics Engineer to serve as a technical Subject Matter Expert (SME) for the development of…
Business Unit: Cubic Defense Company Details: When you join Cubic, you become part of a company that creates and delivers technology solutions in transportation to make people’s lives easier by simplifying their daily…
Date Posted: 2026-09-16

 Country: United States of America

 Location: US-IA-CEDAR RAPIDS-130 ~ 5350 C Ave NE ~ BLDG 130

 Position Role Type: Onsite

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This role involves translating system-level requirements into FPGA specifications and performing hands-on FPGA design, verification, and integration for mission-critical systems. The engineer will work with Xilinx or Intel platforms, manage system architecture, and collaborate with cross-functional teams to validate hardware and firmware interactions.
We are seeking a highly experienced and driven Principal Engineer to lead the end-to-end design, development, integration, and validation of advanced ATE test hardware. This senior technical role combines deep hands-on…
Job Title: Senior Digital Design Engineer Role Summary: Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications.…
Leads the integration of quantum computing hardware systems, translating architecture into scalable photonics/electronics designs and coordinating cross-functional teams to build, test, and deploy fault-tolerant quantum computers.
Principal engineer designing and building automated diagnostics software to monitor and troubleshoot AI hardware clusters and blade servers.
Principal FPGA Design Engineer Location: Oxford Permanent Oxford Nanopore Technologies : Our goal is to bring the widest benefits to society through enabling the analysis of anything, by anyone, anywhere. The company…
Are you passionate about pushing the boundaries of technology and solving complex challenges? At Nokia, we're looking for innovative minds to join our Applied Research & Development (AR) and Digital Hardware…
OnSemi is seeking a Sr. Principal Digital design, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products, LED…
Date Posted: 2026-09-15

 Country: United States of America

 Location: US-MA-TEWKSBURY-TB1 ~ 50 Apple Hill Dr ~ ASSABET BLDG

 Position Role Type:…
Date Posted: 2026-09-15

 Country: United States of America

 Location: US-TX-MCKINNEY-513WA ~ 2501 W University Dr ~ WING A BLDG

 Position Role Type:…
About NSING : As part of Nations Technologies Group, NSING was founded in 2018 in Singapore bringing high-performance semiconductor products and solutions to global semiconductor industry. Our products includes General…
Application close date: 10/6/2026 At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems…
RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 25% of the Time Description At Northrop Grumman, our employees have incredible…
Senior digital design engineer at Astera Labs owning complex digital blocks for AI connectivity silicon — from micro-architecture and RTL implementation through timing closure, DFT, verification support, and silicon bring-up — targeting PCIe Gen 6/7, CXL, UALink, Ethernet, and DDR protocols on sub-7nm nodes using Cadence/Synopsys flows.
Architects and implements complex digital blocks for Astera Labs' AI connectivity silicon, owning designs from micro-architecture and RTL through timing closure, DFT, verification, and post-silicon bring-up for protocols like PCIe Gen 6/7, CXL, UALink, UCIe, Ethernet, and DDR, using Cadence/Synopsys flows on advanced CMOS nodes.
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