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Designs and validates next-gen robotic automation systems, integrating hardware and software to streamline deployment for real-world use cases.
Designs and validates FPGA logic for networking hardware using Verilog/VHDL, vendor tools (Vivado/Quartus), and industry-standard flows to ensure first-pass success.
Designs high-speed analog/mixed-signal I/O circuits (SerDes, memory PHYs, chip-to-chip links) for next-gen AMD processors using advanced FinFET nodes and Cadence tools.
Responsibilities Architect, design, and build our second generation hardware platform from concept to production Own full system design including PCB layout, component selection, power management, and thermal…
Designs user experiences for Google’s Pixel hardware products, focusing on innovation and usability while mentoring junior designers.
Role Overview We are looking for a Director of ASIC Design to drive the design, development, verification, and execution of high-performance AI inference chips. This role requires deep technical expertise in ASIC…
Build FPGA-based ultra-low-latency trading systems in Verilog/VHDL, automate RTL generation, and collaborate on real-time capital-markets infrastructure.
Develop FPGA software for video and image processing systems using HDL and related tools to build high-precision display, camera, and computer solutions.
Designs and tests embedded hardware systems, creates schematics and documentation, and collaborates with cross-functional teams to bring products from concept to production.
Designs and maintains RF hardware and systems for a defence contractor, including RF design, testing, debugging, and real-time system integration.
Design and implement the clocking logic for NVIDIA’s next-gen networking chips, writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, and domain-crossing infrastructure.
Lead the RTL design and implementation of clocking logic for NVIDIA’s next-gen networking chips, including PLL integration, clock distribution, and reset synchronization, guiding the team from spec to silicon.
Lead APQP/PPAP processes for medical-electronics products, ensuring regulatory compliance and smooth NPI through DFMEA, PFMEA, and supplier audits.
Install, maintain, and troubleshoot hardware in a large-scale data center, supporting the technical team with racking, cabling, and equipment diagnostics.
Oversee operational delivery and governance for OpenAI's third-party infrastructure partners, ensuring reliability and performance of cloud and compute services that power AI workloads.
Lead WHOOP’s hardware product strategy, guiding a team to design and launch wearable devices that unlock human performance and health insights.
Hardware Quality Engineer at Lambda ensures AI cloud infrastructure reliability by tracking issues, performing root cause analysis, and improving RMA processes for GPU/data-center hardware.
Intern designs FPGA/ASIC solutions for ultra-low-latency trading systems, writing and verifying RTL in SystemVerilog and bringing designs up on live hardware.
Design and verify custom silicon chips for next-generation data storage hardware, using RTL, Verilog/SystemVerilog, and digital logic while collaborating with cross-functional engineering teams.
Design and verify custom silicon and hardware for next-generation data storage devices, collaborating across ASIC, firmware, and systems engineering teams using RTL, Verilog, and embedded C/C++.
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