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Senior Manager, Hardware Engineer, OLYSENSE
Leads the hardware engineering section (5-6 engineers) for Olympus's OLYSENSE Hub, a cloud-connected, AI-enabled regulated medical device, owning the COTS computing platform roadmap from architecture and supplier/OEM integration through reliability, EMC/safety compliance (IEC 60601), production transfer, and lifecycle sustainment.
Praktikum Hardware-Entwicklung, Validierung und Simulation, Wireless Charging 22kW+ (m/w/d)
Six-month hardware engineering internship (starting Feb/Mar 2027) at MAHLE in Stuttgart on 22 kW+ wireless EV charging systems. Day to day: PCB design and schematic capture with Altium, power-electronics simulation in LTspice, prototyping, and hardware testing/debugging.
Internship in Hardware Development, Validation and Simulation, Wireless Charging 22kW+ (m/f/d)
A 6-month internship at MAHLE in Stuttgart supporting hardware development, validation and simulation for 22kW+ wireless charging: designing PCBs and schematics in Altium Designer, running power electronics simulations in LTspice, and building, testing and debugging hardware prototypes.
Hardware Design Engineer (FPGA)
Job Req ID: 30323 About Supermicro: Supermicro® is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and…
Intern, RFIC Design - Fall 2026
A Fall 2026 RFIC Design intern at pSemi (a Murata company) in San Diego assists engineers validating, characterizing, and testing high-performance RF front-end ICs for 5G/6G and LTE-A products. Day-to-day work involves RF lab measurements, building custom test benches, documenting results, and Cadence simulation/layout.
Líder técnico hardware
Hardware technical lead at Capgemini Engineering in Barcelona, guiding automotive electronics R&D projects from architecture through validation: hardware architecture decisions, schematic/PCB design oversight, team coordination, and compliance with EMC and functional-safety (ISO 26262) standards using tools like Altium or Mentor Graphics.
Directeur de Programme Semi-conducteurs
Capgemini Engineering, leader mondial des services d'ingénierie , rassemble des équipes d'ingénieurs , de scientifiques et d'architectes pour aider les entreprises les plus innovantes dans le monde à libérer leur…
Stage 6 mois - Ingénieur.e Électronique de Puissance (F/H)
Raq ID : 530509 Chez Alstom, nous construisons ce dont des millions de personnes dépendent chaque jour : des systèmes de transport ferroviaire qui ne peuvent pas se permettre d'échouer. Nous sommes plus de 85 000…
Technical Staff - Avionics and Hardware-in-the-Loop (HWIL) Lead Engineer
Lead avionics engineering and hardware-in-the-loop (HWIL) test bed development for a portfolio of space mission programs at MIT Lincoln Laboratory: architect flat-sat and real-time simulation environments, verify flight software and avionics hardware before flight, support hands-on assembly/integration/test, and mentor junior engineers. Core work spans embedded avionics, real-time simulation, and
Hardware Engineer, (Defense & Aerospace, North Reading, MA)
Teradyne's Defense & Aerospace Division delivers advanced, mission critical test solutions to military and aerospace customers worldwide. Our comprehensive portfolio supports the entire test lifecycle across factory,…
Jr. FPGA Developer (Compute Test, North Reading)
Junior FPGA engineer in Teradyne's Compute Test Division supporting design, implementation, bring-up, and debugging of FPGA-based solutions for semiconductor test platforms. Day-to-day work spans Verilog/SystemVerilog design, timing closure, lab debugging via JTAG, and TCL/Python scripting, based on site in North Reading, MA.
Hardware/Software Integration Engineer (Compute Test, North Reading)
Hardware/software integration engineer at Teradyne's Compute Test group who owns the seams of a semiconductor test instrument stack — tracing defects end to end from host API and driver through embedded software, HAL, FPGA, and DAC to find root cause. Core toolkit: C/C++, Python, register-level debugging, HDL/FPGA reading, and schematics.
Hardware Interface Project Lead (Teradyne, San Jose, CA)
Leads end-to-end execution of hardware interface development programs for Teradyne's automated test equipment (ATE): planning projects, managing schedules, risks, and change control, and coordinating engineering teams, suppliers, and PCB design work (schematic, layout, SI/PI, DFM). Requires strong high-speed/RF PCB expertise plus MS Project and Excel.
Senior FPGA Design Engineer (MTD, San Jose, CA)
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works…
ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works…