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Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling…
Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation…
Voltai, an early-stage AI startup building world models and agents for hardware/chip design, is hiring a DFT Engineer to own design-for-test architecture and implementation (scan, MBIST, ATPG, boundary scan) on real silicon programs with leading semiconductor companies, while helping its AI learn DFT methodology. Based in Palo Alto; requires 5+ years of DFT experience and tools like Tessent, TestM
Owns emulation and FPGA prototyping for SoC programs at Voltai — building emulator/FPGA platforms, mapping designs with partitioning and timing closure, enabling early software bring-up, and debugging system-scale hardware/software issues while generating data to train Voltai's AI models. Key tools: Palladium/ZeBu/Veloce/HAPS, SystemVerilog, Vivado/Quartus, Python/Tcl/C++.
About Voltai Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems…
Physical Design Engineer at Voltai (Palo Alto, on-site): own chip implementation from netlist to GDSII — floorplanning, placement, CTS, routing, and timing/power closure — on production silicon programs while helping Voltai's AI learn expert physical design decisions. Core tools: Cadence Innovus or Synopsys Fusion Compiler/ICC2, Tcl, Python.
Design and own RTL for production silicon at Voltai — microarchitecture and SystemVerilog implementation for IP blocks, driving lint/CDC, synthesis, and timing closure, and debugging across simulation, emulation, and silicon, while helping train Voltai's AI to write and review chip designs.
The Care Manager l-TCL assures that individuals and families with special health care needs receive integrated whole-person care management, including coordinating across physical health, behavioral health, pharmacy…
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google…
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Designs and implements signal-processing and communications algorithms as resource-optimized RTL (VHDL/Verilog/SystemVerilog) on FPGAs for Xona's LEO PNT satellites — covering fixed-point DSP design, timing/power optimization, verification via testbenches and Python/C++ reference models, and lab/HIL bring-up.
Junior (0-1 years) software engineer on Cadence's Innovus placement team in South Korea, developing and maintaining placement-related features of a leading post-end-of-line digital design (EDA) platform. Core work is C/C++ development and debugging in a Unix/Linux environment.
Software Engineer II on Cadence's Innovus placement team in South Korea, developing and maintaining placement features for a leading digital design (EDA) platform. Day-to-day work centers on C/C++ development and debugging in a Unix/Linux environment, with an emphasis on algorithms and optimization.
We are seeking a diligent SoC/MCU Verification engineer to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase…
负责数字IC模块/SoC级 低功耗设计流程，编写与维护 UPF（Unified Power Format），完成电源域划分、隔离/电平转换/电源开关等低功耗结构的实现与检查。 负责 SpyGlass CDC/RDC/Lint 检查，分析跨时钟域路径，制定 CDC 约束与豁免策略，推动设计端修复亚稳态与复位域问题。 负责 逻辑综合（Synthesis），完成 RTL…
The candidate is expected to be responsible for following tasks: Participate in complex Chip DFT/DFD feature and architecture definition Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test…
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
Main Accountabilities Create and manage data flow diagrams to track personal data across systems. Prepare and update Records of Processing Activities (RoPA) in line with regulatory requirements. Work on Project for…
SAIC is seeking an experienced FPGA/Embedded-Systems Engineer to design, verify, and integrate advanced digital processing architectures. The ideal candidate will possess strong FPGA development experience using VHDL…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
