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Job Description • Lead innovation and enablement of custom design methodology and solutions to address critical design challenges in leading-edge technologies. • Collaborate with EDA partners to deliver innovative and…
Einleitung Verstärke unseren Bereich Hardware Entwicklung in Berlin (Deutschland) zum nächstmöglichen Zeitpunkt. Aufgaben Hardware-Entwicklung: Unterstützung bei der Entwicklung und Integration von innovativen…
Einleitung Verstärke unseren Bereich Softwareentwicklung in Berlin (Deutschland) zum nächstmöglichen Zeitpunkt. Aufgaben CI/CD-Automatisierung: Konzeption, Aufbau und Pflege automatisierter GitLab CI/CD-Pipelines für…
Who we are looking for Required Education and Experience B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline 5+ years of experience in Digital IC Design with strong expertise in RTL…
作為華邦的(竹北) CAD AI Engineer ， 【工作內容】 1. 建立 RAG 架構（文件 / Jira / log / engineering data） 2. 開發內部 AI 工具（knowledge assistant / debug assistant / automation） 3. 整合 LLM（如 Gemma、LLaMA）至工程 workflow 4. 設計資料處理流程（text / log / 文件） 5.…
Who we are looking for Master’s or Bachelor’s degree in Electrical Engineering with emphasis in Analog Mixed-Signal Verification or a similar specialty, as well as at least 10 years of proven industry experience.…
Overview of Role As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be…
Leads power integrity analysis for AI connectivity ASICs, ensuring stable power delivery and reliability through IR drop and electromigration sign-off from floorplan to tapeout.
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.
Glance AI is an AI commerce platform shaping the next wave of e-commerce with inspiration-led shopping, less about searching for what you want and more about discovering who you could be. Operating in 140 countries,…
Designs and maintains load-balancing solutions for high-traffic apps using Nginx and related tools, automating infrastructure and scripting workflows.
Front-end ASIC design engineer on Apple's Pixel IP team, writing RTL and micro-architectural specs for high-performance, low-power image/video processing pipelines in next-gen SoCs.
Front-end ASIC Design Engineer responsible for designing high-performance, power-efficient pixel processing engines for Apple's SoCs using RTL or high-level synthesis methodologies.
Lead development of advanced communications systems (satellite, cellular, private networks) using board-level electronics, FPGA, and signal processing expertise.
Contexte : Pour accompagner la croissance de notre entité spécialisée en ECM/GED, nous recherchons notre futur chef de projet F/H capable de travailler en autonomie dans le cadre des projets de développement…
The Sr. Staff SoC Power & Performance Architect will work on-site in Austin to drive power and performance architecture for Ambiq's low-power semiconductor solutions. The role involves collaborating across cross-functional teams to advance energy-efficient chip design for AI-powered edge applications.
Designs ultra-low-power embedded memory (SRAM/Register File) circuits and compilers for AI edge chips, optimizing for area, speed, and sub-threshold operation while collaborating with foundries and validation teams.
Leads power validation and optimization for ultra-low-power SoCs, designing validation plans and automation tools while collaborating with cross-functional teams to ensure industry-leading energy efficiency.
Lead validation and optimization of ultra-low-power wireless radios (BLE, Bluetooth Classic, 802.15.4) for next-gen SoCs, defining test methods and automating RF characterization in a lab setting.
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