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What you will be doing Responsible for the design/lead of the Power Management IC deliverable for LTE, GNSS, WiFi, Bluetooth, Zigbee, and other communication systems. The ideal candidate can design Analog/Power…
What you will be doing: Responsible for high-performance and low power RFIC Transceiver Design for LTE, GNSS, WiFi, Bluetooth, Zigbee, and other communication systems. Be the Technical Lead for a team of talented and…
What you will be doing: Responsible for high-performance and low power. Receive & Transmit Baseband analog blocks, as well as Power Management building blocks for LTE, GNSS, WiFi, Bluetooth, Zigbee, and other…
About the role We are seeking a Senior Field Applications Engineer to drive customer adoption of Ferric’s IVR products with leading AI semiconductor companies, hyperscalers, ODMs, and advanced compute platform teams.…
Leads the design and optimization of high-performance, low-power standard cell libraries and custom digital circuits, including transistor-level innovation, arithmetic block architecture, and circuit verification across PVT corners. Focuses on reliability sign-off, low-power innovations, and mentoring engineers in advanced CMOS technologies.
Job Summary: We are seeking an experienced IO Circuit Design Engineer with 5-8 years of expertise in designing and validating high-performance I/O circuits for advanced semiconductor SoCs. The role involves developing…
About GlobalFoundries GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers…
How would you like to join Arm at a time of transformation in our industry? Our memory development group comprises some of the industry’s leading experts in deep submicron circuit design. This position is a rare…
Principal Product Engineer at Cadence to drive backend design flows in Virtuoso for advanced process nodes, combining IC layout, automation, and customer engagement.
NXP’s Austin Memories team is seeking an experienced memory circuit design engineer for our SRAM and ROM internal memory compiler designs. Our team is part of the Design Enablement/Foundation IP organization within the…
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We are looking for an experienced Sr Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications . The role involves defining, developing,…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Role Overview & Objective We are looking for a motivated SRAM Circuit Design Engineer to join our…
Lead the design and automation of RF, analog, and mixed-signal test-site layouts for next-gen semiconductor processes using Cadence Virtuoso and SKILL scripting.
Designs high-performance analog/mixed-signal circuits (PLLs, ADCs/DACs, RFIC) using Cadence Virtuoso, Spectre, and Mentor Calibre, with multi-node process experience from 28nm to 7nm.
Designs and verifies chip-level layout for high-performance memory-interface chips using Cadence Virtuoso and Calibre in 22nm–7nm nodes.
Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area: Engineering Services Group, Engineering Services Group > Mask Layout Design General Summary: Job Summary: We are looking for a…
An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Lead the design of high-performance power-management ICs in advanced CMOS, owning architecture, layout, and silicon validation for next-gen PMICs used in data centers and energy systems.
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