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An ASIC physical design intern at NVIDIA works on chip implementation tasks from RTL freeze to tapeout, focusing on synthesis, verification, constraints, timing closure, and methodology development for high-frequency, low-power designs.
An intern ASIC Physical Design Engineer at NVIDIA works on chip implementation from RTL freeze to tape-out, handling synthesis, verification, constraints, timing closure, and methodology development for high-performance, low-power digital chips.
Position Overview: We are looking for an experienced Synthesis Methodology Engineer to own and drive RTL synthesis methodologies across our AI SoC development projects. You will be responsible for developing,…
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the…
Position Summary : TCL North America is seeking a highly accountable, results-driven E-Commerce & Marketplace Manager to own the day-to-day execution and performance of the company's e-commerce channels,…
The Firmware Engineer will design and verify complex firmware solutions for FPGAs, SOCs, and CPLDs to support aerospace and defense programs. This onsite role involves generating requirements, creating HDL-based digital circuits, and performing laboratory testing.
The CPU Physical Design Engineer will perform physical design implementation of custom CPUs from RTL to GDS, including synthesis, floor planning, and timing closure. The role involves collaborating with cross-functional teams to optimize CPU microarchitecture for power, frequency, and area.
Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in developing and integrating logic designs into complex System-on-Chip (SoC) architectures. Your…
Designs and implements high-performance, low-power memory logic from netlist to GDSII, focusing on timing closure, power integrity, and manufacturability in advanced process nodes.
The Platform Test Automation Engineer will design, automate, and execute tests for Nokia's Ethernet and optical router components in a Linux-based environment. The role involves collaborating with cross-functional teams to validate hardware and software features using scripting languages and specialized networking test equipment.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are a small group of individuals designing among the most complex chip in the world getting into the…
This CAE Engineer role focuses on structural simulation and durability analysis of suspension and steering systems using FEA tools. The position involves optimizing designs through DOE studies, automating workflows with Python or TCL, and collaborating with cross-functional teams to ensure vehicle performance and quality.
Lead AI-driven automation for advanced semiconductor package design, optimizing routing, placement, and signal integrity using EDA tools and machine learning.
Define and optimize power methodologies for AMD’s next-gen CPU/GPU/SOC designs, driving performance/watt from synthesis to route using tools like PrimePower and scripting in Perl/Tcl/Python.
We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 7 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles,…
Design and verify timing for Google’s TPU chips, ensuring high-performance AI hardware meets sign-off requirements and architectural goals.
About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
Designs and verifies low-power digital subsystems and mixed-signal SoCs using SystemVerilog/VHDL, synthesis, and verification tools in a semiconductor company.
Principal Engineer builds AI-driven EDA workflows to automate ASIC physical design, using LLMs and agentic tools to reduce design cycles and improve timing/congestion outcomes.
Digital Design Engineer responsible for SoC/MCU digital sub-circuit development including RTL coding in Verilog/SystemVerilog, synthesis, STA, formal verification, DFT, and post-silicon validation at NXP's Catania site.
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