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We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Lead a team to design and deliver next-gen processor and SoC IP, driving RTL development, verification, and silicon execution while optimizing power, performance, and area.
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL, and PPA trade-offs with cross-functional teams.
Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Designs ASIC microarchitectures using Verilog HDL, leads RTL architecture discussions, and ensures quality through synthesis, timing, and power analysis in hardware development.
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Principal Digital Engineer designs and implements DFT/Scan for automotive PMIC chips, working with RTL, synthesis, ATPG, and test teams to meet ASIL-B/D requirements and validate patterns on silicon.
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Principal Engineer defines and leads SoC/MCU architectures for India-focused semiconductor platforms, coordinating RTL design, verification, firmware, and validation to deliver first-pass silicon for automotive, industrial, and emerging domains.
Design a radiation-tolerant RISC-V microcontroller ASIC for CERN’s particle physics detectors using 65/28 nm CMOS, RTL-to-tapeout with fault-tolerant techniques and post-silicon validation.
Design and deliver FPGA-based systems using Xilinx/Intel tools, RTL/Verilog/VHDL, and collaborate across teams to close timing and debug prototypes for clients in high-speed electronics.
Design high-performance Ethernet MAC engines and network datapaths for AI-driven ASICs, ensuring line-rate performance and protocol compliance using SystemVerilog and AI-assisted flows.
Design and implement memory controllers, hierarchies, and near-memory accelerators for AI-driven ASICs, optimizing bandwidth, latency, and power for ML workloads using SystemVerilog and AI-assisted flows.
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
Designs and verifies safety-critical GPU hardware for automotive and robotics, ensuring compliance with ISO 26262 through safety analyses and documentation.
Build AI-powered automation tools to streamline Arm’s hardware design and verification workflows, integrating EDA tools and AI models like OpenAI Codex to cut cycle time and debug effort.
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