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The role involves validating and debugging USB host/device functionality, HPS boot flows, and peripheral integration for next-gen FPGA SoC devices, ensuring reliability and customer readiness through hands-on SoC bring-up, protocol validation, and advanced silicon debugging.
Graduate engineer validates next-gen FPGA SoC USB subsystems in lab, running tests, debugging silicon, and automating validation with Python/TCL.
Job Details: Job Description: Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip.…
Designs and develops advanced FPGA-based embedded systems and AI/ML algorithms for semiconductor equipment, focusing on heterogeneous processing architectures, IP core development, and troubleshooting complex hardware/software issues.
Develops and validates semiconductor PDKs, automates library workflows, and optimizes physical design for advanced chip manufacturing using Synopsys/Cadence tools.
An internship designing RTL for HBM SoC logic die, collaborating with architecture/verification teams to implement high-performance SoC solutions and integrating AI-driven tools into workflows.
Network Solutions Architect responsible for solution design, client presentations, RFP/tender responses, and technical architecture governance for large accounts in Singapore, focusing on enterprise networking technologies including SDDC, SD-WAN, wireless, firewalls, and load balancing.
Leads IC backend physical design tasks, including floorplanning, clock/power architecture, and tapeout, collaborating with front-end teams to ensure chip design integrity.
R&D engineer responsible for physical design and implementation of high-performance System-On-Chip ASICs (500M–800M gates) at 5nm/3nm/2nm nodes using commercial and in-house EDA tools, collaborating with RTL teams and supporting customers.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Videomaker mobile role focusing on mobile video capture and editing for social media using Capcut, Premiere, and AI tools, supporting strategic clients.
Lead a team to design and integrate ASIC/SOC components, focusing on power and clock management, while collaborating with cross-functional hardware and software teams.
Qualis LLC is seeking an experienced FPGA/Digital Design Engineer to develop high-performance FPGA solutions for advanced RF and software-defined radio systems. The ideal candidate is a hands-on AMD/Xilinx FPGA…
Senior/Principal Physical Design Engineer at Fractile, responsible for end-to-end ASIC/SoC physical design implementation (floorplanning, placement, CTS, routing, sign-off) using EDA tools like Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre, optimizing PPA metrics and collaborating with cross-functional teams.
Designs and integrates high-performance, low-power pixel processing engines for Apple’s SoCs, writing RTL and collaborating with verification and physical design teams.
Lead AI-driven automation for advanced semiconductor packaging, building workflows that optimize substrate, interposer, and bridge interconnect designs using EDA tools and ML frameworks.
Kandou is a semiconductor company pioneering high-performance interconnect and chip-to-chip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and…
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
The Physical Design Engineer will manage the end-to-end physical implementation of System-on-Chips (SoCs) for drone autonomy technology, covering tasks from synthesis to GDSII sign-off. The role involves utilizing industry-standard EDA tools to ensure timing closure, power efficiency, and physical verification.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
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