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About Alpha Design AI Alpha Design AI builds ChipAgents™, the industry's first AI-agent platform that accelerates RTL design and verification. We serve semiconductor innovators - from fast-growing startups to…
Design and verify FPGAs for spacecraft test infrastructure, bridging hardware interfaces and enabling real-time functions like packet timestamping and command scheduling.
Designs high-performance PCIe Gen6/Gen7 switch ASIC IP using SystemVerilog, focusing on RTL implementation, timing closure, and architecture for next-gen connectivity solutions.
Principal Engineer designs and runs pre-silicon verification for DDR, HBM, and GDDR memory controller IP using SystemVerilog and UVM, with coverage-driven test suites and regression monitoring.
Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.
Principal PCIe logic engineer designs next-gen PCIe IP in SystemVerilog, collaborates with verification teams, and prototypes on FPGAs.
Design and optimize high-performance processor chips using advanced EDA tools, focusing on synthesis, place-and-route, timing closure, and ECOs for server, 5G/6G, and networking applications.
Designs and verifies high-speed USB 2.0 and eUSB2 chips, writing RTL code and debugging mixed-signal circuits for next-gen AI and IoT solutions.
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…
Principal Logic Design Engineer Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our…
Verify next-gen x86 CPU cores by writing C++/SystemVerilog tests and checkers, debug RTL issues, and drive coverage closure in a hybrid Austin office.
Designs and enhances SystemVerilog/UVM testbenches to verify PCIe subsystem features, collaborating with architects and engineers to ensure robust RTL designs and memory subsystem performance.
Sr. Principal Digital Designer Location: Bangalore Time Type: Full time Job Description Role Summary We are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital…
Designs and validates FPGA logic for networking hardware using Verilog/VHDL, vendor tools (Vivado/Quartus), and industry-standard flows to ensure first-pass success.
Staff Engineer, Digital Design Engineering Location: US, MA, Chelmsford, Elizabeth Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that…
Staff Digital Design Engineer Location: Germany, Munich, Seidlstr Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical…
Role Overview We are looking for a Director of ASIC Design to drive the design, development, verification, and execution of high-performance AI inference chips. This role requires deep technical expertise in ASIC…
Design and implement the clocking logic for NVIDIA’s next-gen networking chips, writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, and domain-crossing infrastructure.
Lead the RTL design and implementation of clocking logic for NVIDIA’s next-gen networking chips, including PLL integration, clock distribution, and reset synchronization, guiding the team from spec to silicon.
Designs and implements C-based tests for wireless SoC verification and power analysis, collaborating across chip disciplines to ensure functional silicon for Apple products.
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