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Designs and verifies digital RTL subsystems for semiconductor products, using SystemVerilog/Verilog and collaborating with architecture and verification teams.
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms.…
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Designs and verifies mixed-signal ICs, building simulation environments and automated regressions to ensure silicon meets specs before tapeout and aligns with customer needs.
Intern designs FPGA/ASIC hardware for ultra-low-latency trading systems, writing RTL in SystemVerilog, verifying with vendor tools, and deploying to live silicon.
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Design and verify custom TPU silicon for Google’s AI workloads using SystemVerilog/UVM, driving full verification cycles from planning to tape-out.
Lead digital design for advanced RAIN RFID reader chips, owning RTL through tapeout and silicon validation while mentoring engineers and improving ASIC flows.
Verify next-gen PCIe controller subsystems for AMD’s SoCs, using UVM, SystemVerilog, and low-power flows to ensure performance and power targets for AI, gaming, and server chips.
Design and develop DSP blocks for quantum computing systems using ASIC flows, RTL, and EDA tools while collaborating with cross-functional teams.
Design and optimize FPGA/SoC solutions for high-performance digital signal processing and RF applications using Xilinx devices and Vivado.
Design and deliver FPGA-based systems using Xilinx/Intel tools, RTL/Verilog/VHDL, and collaborate across teams to close timing and debug prototypes for clients in high-speed electronics.
Design high-performance Ethernet MAC engines and network datapaths for AI-driven ASICs, ensuring line-rate performance and protocol compliance using SystemVerilog and AI-assisted flows.
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
Design and implement memory controllers, hierarchies, and near-memory accelerators for AI-driven ASICs, optimizing bandwidth, latency, and power for ML workloads using SystemVerilog and AI-assisted flows.
Design and verify PCIe interconnect IP for AMD’s GPUs, APUs, servers, and consoles using UVM/SystemVerilog, collaborating with global teams.
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
Designs and implements ASICs for quantum computing systems, focusing on DSP blocks and RTL development while collaborating with cross-functional teams.
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