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FPGA Associate (Summer 2027)

Open 31d North AmericaInternship

A 12-week, salaried associate role for new grads at satellite maker Astranis in San Francisco: you'll write RTL for FPGAs, work across multiple toolchains, interface FPGAs with high-speed data converters and memories, and write test software alongside electrical and software engineers. Requires Verilog/SystemVerilog proficiency and U.S. person status.

FPGA SystemVerilog Tcl Uvm Verilog

FPGA Associate (Winter 2027)

Open 31d North AmericaInternship

A 12-week salaried associate role at satellite maker Astranis in San Francisco for new grads: designing RTL for FPGA-targeted applications, interfacing FPGAs with high-speed data converters and memories, and writing software to test RTL in hardware alongside electrical and software engineers. Core tools are Verilog/SystemVerilog and FPGA toolchains like Xilinx Vivado.

FPGA SystemVerilog Tcl Uvm Verilog

FPGA Intern (Summer 2027)

Open 31d North AmericaInternshipIntern

A 12-week summer internship in San Francisco working on FPGA development for Astranis satellites: writing RTL, interfacing FPGAs with high-speed peripherals like data converters and memories, and testing RTL in hardware alongside electrical and software engineers.

FPGA SystemVerilog Tcl Uvm Verilog

29 – 29 $ / hr

FPGA Intern (Winter 2027)

Open 31d North AmericaInternshipIntern

A 12-week, hourly internship on Astranis's FPGA team in San Francisco: the intern writes RTL for satellite-targeted FPGAs, interfaces them with high-speed data converters, memories and MCUs, and builds test software alongside electrical and software engineers. Open to current students with US citizenship or a green card.

FPGA SystemVerilog Tcl Uvm Verilog

29 – 29 $ / hr

Hudson River Trading

Hardware Design Engineer - 2027 Grads

Open 54d North AmericaInternshipIntern H-1B sponsor history

Entry-level (2027 grads) hardware design engineer at a proprietary trading firm, designing FPGA/ASIC logic in SystemVerilog to build low-latency compute engines that transform market data in real time. Core stack: SystemVerilog, FPGA/ASIC tools, computer architecture, with C++/Python on Linux.

AI Automation C++ FPGA Linux +4 skills

300K – 300K $

Hudson River Trading

Hardware Engineer Internship - Summer 2027

Open 54d North AmericaInternshipIntern H-1B sponsor history

Summer 2027 hardware engineering internship at Hudson River Trading, where interns design and verify FPGA/ASIC compute engines for low-latency algorithmic trading — writing SystemVerilog design code and Python-based modeling/verification environments on critical, real-time trading infrastructure.

AI Asic Automation C++ FPGA +5 skills

302K – 302K $

Digital ASIC Design Engineer

Open 17d RemoteEurope

Hands-on digital IC design role in Nuremberg: flow system requirements into architecture, write RTL and SystemVerilog testbenches, and drive synthesis, STA, timing closure, and gate-level simulation for DSP/mixed-signal THz interconnect ASICs, plus post-tapeout lab support. Core stack: SystemVerilog, Tcl/Python scripting, bus interfaces, and Cadence tools (XCelium, Genus, Tempus).

AI Asic Bash Cmos Fiber +8 skills

PMU Digital Design Verification Intern (m/f/d)

Open 17d InternshipIntern

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling…

OOP Perl Python SystemVerilog Tcl +3 skills

Hardware Developer- New Graduate

Open 52d North AmericaJunior

Quantiq specializes in high frequency derivatives trading in the largest markets worldwide. Our approach is rigorous and pragmatic, driven by technological expertise and analytics, informed by real-world experience. We…

AI Analytics C++ Express.js FPGA +9 skills

Hardware Developer

Open 52d North America

Designs, optimizes, and maintains low-latency network paths and a custom FPGA data processing platform for a high-frequency derivatives trading firm, writing Verilog/VHDL digital logic, C++ network protocol drivers, and profiling/debugging for maximum performance.

AI Analytics C++ FPGA SystemVerilog +2 skills

ASIC Design Verification Technical Lead, High-Speed DSP

Open 17d MENA, North AmericaLead Licensed UK sponsor Licensed NL sponsor Denmark Fast-track company

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…

AI Asic Cloud GCP Machine Learning +6 skills

Wireless SoC Design Verification Engineer

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible various aspects of wireless silicon development with a particular emphasis on highly energy…

Rtl SystemVerilog

Ingénieur de Vérification Fonctionnelle FPGA / ASIC Numérique (H/F)

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Ingénieurs de…

Bash Cmos FPGA Linux Python +4 skills

Architecture Développement ASIC Numérique / FPGA (H/F)

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Architectes en…

Bash Cmos FPGA Linux Python +4 skills

Responsable de Vérification Fonctionnelle ASIC / FPGA Numérique (H/F)

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Responsables de…

Bash Cmos FPGA Linux Python +4 skills

SoC RTL Performance Analysis Engineer

Open 129d HybridNorth America Ireland permit employer

Job Description: Passionate in analyzing performance bottlenecks and driving architectural improvements? Eager to expand into building SoC platforms for performance verification analysis? Arm’s System-on-Chip (SoC)…

Accessibility AI Automation C++ Git +7 skills

198K – 268K $

Senior RISC-V Digital IP Design Engineer

Open 37d EuropeSenior

What is this role about? Join onsemi’s new and growing RISC-V division and help define and implement configurable and customizable RISC-V CPU IP for real embedded products. You will participate in the CPU design…

AI Firmware Rtl SystemVerilog Uvm +1 skills

NXP Semiconductors

Senior HW Digital Design Verification Engineer

Open 17d EuropeSenior Licensed NL sponsor

Job Summary NXP Semiconductors Netherlands B.V. is seeking a highly skilled and experienced Senior HW Digital Design Verification Engineer to join our dynamic team. In this role, you will be responsible for defining…

Perl Python SystemVerilog Tcl Uvm

ASIC Digital Design, Staff Engineer- 19010

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…

Bash Ethernet PCIe Perforce Perl +3 skills

ASIC Digital Design, Sr Staff Engineer- 19061

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…

Bash Ethernet PCIe Perforce Perl +3 skills