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Leads verification strategy for a high-performance CPU cache-coherent interconnect, defining test plans, assertions, and coverage to ensure protocol correctness and subsystem integration across multiple interfaces.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. As a Verification Application Engineer (AE) at Cadence you will be responsible for leading customer…
Design and verify high-speed memory interface logic in Verilog/SystemVerilog, collaborating with teams to close timing, power, and silicon validation for HBM products.
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, synthesis, and verification flows.
Staff Subsystem Design Engineer Job Overview Arm’s IP and Technology team in Solutions Engineering department evelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud…
Architect and optimize the next-generation SystemVerilog compiler for Xcelium, enabling faster verification of billion-gate AI and hyperscale chip designs using C++ and compiler theory.
Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
Design and run verification tests for next-gen DRAM and memory chips using SystemVerilog/UVM, debug failures, and automate flows to ensure silicon meets specs.
Designs high-speed digital circuit boards for military radar systems using CAD tools, power/signal integrity analysis, and embedded processors; collaborates on FPGA-based designs and hardware testing.
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
About the role Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing. What you'll do Micro-architect and own…
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across RTL, verification, and physical design to tape out custom ASICs.
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
Designs and writes advanced circuit-engineering free-response questions to stress-test AI models, requiring a PhD in EE and 5+ years of shipped analog/digital/power/RF designs.
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.
Tech Lead Design Engineer Location: San Jose, California, United States Department: Board Validation Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By…
Designs and verifies RTL for AI NPUs, focusing on SoC blocks like interfaces, power management, and clocking using Verilog/SystemVerilog and scripting (Python/Tcl).
Contract FPGA engineers to design and implement Verilog/VHDL for satellite telecoms projects using Xilinx ISE and SystemVerilog.
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