Tech jobs

Open 133d North AmericaFull-time

FPGA Engineer

Firmware FPGA SystemVerilog Tcl Uvm +1 skills

Designs, verifies, and tests FPGA-based RTL for satellite systems, collaborating with hardware, software, and DSP teams to meet performance and radiation-mitigation requirements.

140K – 205K $

Open 40d North AmericaFull-timeSenior

Senior FPGA Engineer

C++ Firmware FPGA SystemVerilog Tcl +2 skills

Senior FPGA Engineer who architects, designs, verifies, and tests RTL for FPGAs in spacecraft and ground stations, including software-defined radios, avionics, and radiation mitigation schemes. Day-to-day work spans Verilog/SystemVerilog, C/C++ bit-accurate modeling, and Xilinx toolchains in close collaboration with DSP and embedded software teams.

175K – 240K $

Open 31d North AmericaInternship

FPGA Associate (Summer 2027)

A 12-week, salaried associate role for new grads at satellite maker Astranis in San Francisco: you'll write RTL for FPGAs, work across multiple toolchains, interface FPGAs with high-speed data converters and memories, and write test software alongside electrical and software engineers. Requires Verilog/SystemVerilog proficiency and U.S. person status.

2K – 2K $

Open 31d North AmericaInternship

FPGA Associate (Winter 2027)

A 12-week salaried associate role at satellite maker Astranis in San Francisco for new grads: designing RTL for FPGA-targeted applications, interfacing FPGAs with high-speed data converters and memories, and writing software to test RTL in hardware alongside electrical and software engineers. Core tools are Verilog/SystemVerilog and FPGA toolchains like Xilinx Vivado.

2K – 2K $

Open 31d North AmericaInternshipIntern

FPGA Intern (Summer 2027)

A 12-week summer internship in San Francisco working on FPGA development for Astranis satellites: writing RTL, interfacing FPGAs with high-speed peripherals like data converters and memories, and testing RTL in hardware alongside electrical and software engineers.

29 – 29 $ / hr

Open 31d North AmericaInternshipIntern

FPGA Intern (Winter 2027)

A 12-week, hourly internship on Astranis's FPGA team in San Francisco: the intern writes RTL for satellite-targeted FPGAs, interfaces them with high-speed data converters, memories and MCUs, and builds test software alongside electrical and software engineers. Open to current students with US citizenship or a green card.

29 – 29 $ / hr

Ericsson

Open 112d HybridNorth America Canada LMIA employer

BE CAD Physical Impl and AI Engineer

AI Automation CAD Python Tcl

Build and evolve Ericsson’s FlowJam CAD framework for ASIC physical implementation, integrating AI-driven optimization and partnering with Physical Design teams to improve power, performance, and productivity.

Cerebras

Open 30d HybridNorth AmericaSenior

Senior ASIC RTL Design Engineer, AI Hardware

Agentic AI AI Ccpa Cloud Ethernet +12 skills

Senior front-end ASIC engineer at Cerebras designing the next generations of its Wafer Scale Engine AI chips: owns micro-architecture, RTL development, synthesis, and silicon bring-up while collaborating with verification, physical design, software, and system teams. Core skills: high-performance RTL, chip/IP integration, networking (TCP/IP, RDMA, Ethernet), PCIe/SerDes, Python/TCL.

200K – 290K $

AttoTude

AI Asic Bash Cmos Fiber +8 skills

Digital ASIC Design Engineer

Open 17d RemoteEurope

Germany

Hands-on digital IC design role in Nuremberg: flow system requirements into architecture, write RTL and SystemVerilog testbenches, and drive synthesis, STA, timing closure, and gate-level simulation for DSP/mixed-signal THz interconnect ASICs, plus post-tapeout lab support. Core stack: SystemVerilog, Tcl/Python scripting, bus interfaces, and Cadence tools (XCelium, Genus, Tempus).

Apple

Open 17d InternshipIntern

PMU Digital Design Verification Intern (m/f/d)

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling…

OOP Perl Python SystemVerilog Tcl +3 skills

Ambiq Micro, Inc.

Open 64d North AmericaStaff H-1B sponsor history

Sr. Staff SoC Power & Performance Architect

AI API Automation Claude Code Confluence +8 skills

The Sr. Staff SoC Power & Performance Architect will work on-site in Austin to drive power and performance architecture for Ambiq's low-power semiconductor solutions. The role involves collaborating across cross-functional teams to advance energy-efficient chip design for AI-powered edge applications.

Advanced Micro Devices, Inc

Agentic AI AI Asic Cloud FPGA +4 skills

Sr. FPGA Engineer - Vivado

Open 80d UKSenior

United Kingdom

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…

Advanced Micro Devices, Inc

Open 123d North AmericaLead

SoC Physical Design Implementation Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…

AI Automation Bash CAD Embedded Systems +3 skills

Google

Open 17d North America Licensed UK sponsor Licensed NL sponsor Denmark Fast-track company

ASIC Technology Librarian

AI Asic Cloud GCP Machine Learning +4 skills

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…

ACTIVUS Group

Ingénieur de Vérification Fonctionnelle FPGA / ASIC Numérique (H/F)

HybridEurope

Bash Cmos FPGA Linux Python +4 skills

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Ingénieurs de…

ACTIVUS Group

Architecture Développement ASIC Numérique / FPGA (H/F)

HybridEurope

Bash Cmos FPGA Linux Python +4 skills

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Architectes en…

ACTIVUS Group

Responsable de Vérification Fonctionnelle ASIC / FPGA Numérique (H/F)

HybridEurope

Bash Cmos FPGA Linux Python +4 skills

Dans le cadre du développement de systèmes électroniques complexes dans les secteurs spatial, défense ou industriel, Activus Group recherche pour le compte de son client basé à Toulouse plusieurs Responsables de…

NXP Semiconductors

Open 17d EuropeSenior Licensed NL sponsor

Senior HW Digital Design Verification Engineer

Perl Python SystemVerilog Tcl Uvm

Job Summary NXP Semiconductors Netherlands B.V. is seeking a highly skilled and experienced Senior HW Digital Design Verification Engineer to join our dynamic team. In this role, you will be responsible for defining…

Intel