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LHP Engineering Solutions is a Functional Safety global leader committed to creating safe transportation with developing technologies such as Electric Vehicles, Advance Driver Assistance Systems. At LHP we ensure…
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The Memory Technology Group is at the core of the Legacy Sandisk Engineering Organization. We are building a cutting edge 3D memory in our multiple billion dollars Fab. Our memory provides performance, power, and…
Meet the Team We are part of the Common Hardware Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Designs and optimizes FPGAs and ASICs for SpaceX's Starlink network, using Verilog/SystemVerilog and collaborating with cross-functional teams to enhance satellite and ground infrastructure performance.
Principal Design Verification Engineer at SpaceX to develop and verify next-generation ASICs for Starlink satellites and ground infrastructure, ensuring high-performance connectivity in space and global networks.
Principal Design Verification Engineer at SpaceX designs, verifies, and validates next-generation ASICs and FPGAs for Starlink’s satellite and ground infrastructure, ensuring high-performance connectivity.
Designs and implements FPGAs and ASICs for SpaceX's Starlink network using Verilog/SystemVerilog, collaborating across teams to enhance satellite and ground infrastructure connectivity.
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade silicon for global connectivity.
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade chips that enable global broadband connectivity.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, using SystemVerilog, UVM, and Python to ensure reliable satellite and ground infrastructure connectivity.
Design Verification Engineer at SpaceX developing and testing next-generation ASICs for Starlink's satellite and ground infrastructure using SystemVerilog, UVM, and Python.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
Designs and validates high-bandwidth memory (HBM) and 3D-stacked DRAM architectures, working closely with U.S. customers to solve base-die challenges and optimize next-gen memory products.
Designs 3D-stacked DRAM logic dies and digital IP for DRAM-on-Logic systems, collaborating with U.S. customers and foundries to optimize performance and integration.
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