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Design for Test (DFT) Engineer at Amazon’s Annapurna Labs, building and verifying custom silicon for AWS. Uses Verilog, SystemVerilog, UVM, and scan/debug flows to ensure chip reliability and yield.
- 7+ years of UVM, C, System C, and scripting experience - Deep understanding of digital design principles, timing analysis, and power management techniques. Expertise in pre-silicon performance validation…
Design and verify modem IP and subsystems for Amazon’s LEO satellite network using UVM, SystemC, and Matlab to ensure reliable connectivity for remote users.
Lead ASIC sustaining programs for Amazon’s satellite broadband network, coordinating tape-outs, bring-up, and production validation to ensure yield, cost, and reliability targets.
Leads verification strategy for next-gen semiconductor interconnect products, building UVM/SystemVerilog testbenches and driving silicon success for high-speed digital designs.
Design and validate complex FPGA/SOC systems for critical aeronautics applications using VHDL/Verilog, ensuring compliance with DO-254 and collaborating with hardware/software teams.
Design and validate complex FPGA/SOC designs for critical aerospace systems using VHDL/Verilog and industry tools, ensuring compliance with safety standards.
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.
Design verification engineer building UVM testbenches and test plans for USB controllers (USB3.2, USB2.0) to ensure compliance with industry standards.
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Semiconductor innovation is accelerating faster than ever, driven by AI, advanced computing, automotive…
Lead verification of complex SoC designs using SystemVerilog, UVM, and formal tools; mentor teams and drive coverage closure for memory-IP projects.
Leads verification of complex NAND memory IP blocks using SystemVerilog, UVM, and formal tools, mentors engineers, and drives silicon success for a flash-memory product company.
Was bieten wir Gesundheitsbudget von 300 - 600 € netto pro Jahr: Frei wählbar für Zahnreinigung, Brillen, IGEL Leistungen, Massagen, Zuzahlungen etc. Bewegen und 23 € netto pro Monat erhalten: Mit unserer SportApp…
Architect next-generation pre-silicon verification strategies for complex semiconductor designs, leading simulation, formal, and emulation methodologies to ensure first-pass silicon success.
Senior engineer verifying complex processor designs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness of Network-on-Chip IPs and SoCs.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Verify and validate AMD’s next-gen GPU and SoC designs using SystemVerilog/UVM, emulation platforms, and formal methods to ensure silicon meets performance, power, and functional specs.
Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.
Design Verification Engineer at AMD responsible for verifying custom hardware accelerators for servers, datacenters, and client/embedded markets using advanced ASIC verification techniques and methodologies like UVM and formal verification.
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