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An internship designing RTL for HBM SoC logic die, collaborating with architecture/verification teams to implement high-performance SoC solutions and integrating AI-driven tools into workflows.
Chip Design Verification Engineer verifying and simulating performance and power management IPs using RTL verification methodologies, in close collaboration with design and architecture teams at NVIDIA.
The Research Fellow will conduct research on open-source processor and AI accelerator architectures, focusing on RISC-V designs and EDA toolchains. The role involves designing digital ICs, optimizing hardware workflows, and publishing research findings within an academic environment.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Designs and implements digital blocks and SoC components for next-gen chiplet power delivery systems, using Verilog/SystemVerilog and collaborating with verification and physical design teams.
DRW is a diversified trading firm with over 3 decades of experience bringing sophisticated technology and exceptional people together to operate in markets around the world. We value autonomy and the ability to quickly…
Designs and optimizes ultra-low-latency trading systems and hardware-accelerated components using FPGA, SystemVerilog, and C++ in a proprietary trading environment.
An FPGA intern at DRW designs, tests, and deploys trading-focused hardware solutions using FPGA tools and languages, collaborating with traders and engineers in a 10-week Chicago-based program.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Qualis LLC is seeking an experienced FPGA/Digital Design Engineer to develop high-performance FPGA solutions for advanced RF and software-defined radio systems. The ideal candidate is a hands-on AMD/Xilinx FPGA…
Intern will develop embedded software for satellites, IoT modules, and ground systems using C/C++, embedded Linux, and real-time OSes while collaborating with hardware and operations teams.
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Designs and executes verification testbenches for memory interface chips using System Verilog and UVM to ensure 100% coverage before tape-out.
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
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