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Implementation Engineer, Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware…
Designs and verifies high-speed interconnect protocols (PCIe, CXL, AXI) using UVM and SystemVerilog to ensure ASIC/subsystem correctness before tape-out.
Senior ASIC Implementation Engineer, Low Power AI Location: Markham, Ontario, Canada Department: ASICS Engineering Work Location: onsite Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group >…
Designs and implements mixed-signal IP blocks (DDR, USB, PCI, PLL) using nanometer technologies, focusing on physical design flow, timing closure, and verification to tape out high-quality silicon.
Design and optimize the physical layout of high-speed CPU cores, ensuring timing closure and power-performance-area targets for next-gen Qualcomm chips.
Design verification engineer building UVM testbenches and test plans for USB controllers (USB3.2, USB2.0) to ensure compliance with industry standards.
Design and optimize timing constraints for Qualcomm’s Oryon CPU cores using industry tools like PrimeTime and Tempus, scripting in TCL/Python, and collaborating with RTL and implementation teams.
About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Semiconductor innovation is accelerating faster than ever, driven by AI, advanced computing, automotive…
Designs and verifies analog and mixed-signal ICs to emulate obsolete microcircuits for defense systems, using tools like Verilog/VHDL and Python.
Designs and runs automated and manual tests for embedded storage software, writes test plans in C/C++, and tracks bugs in JIRA to ensure product quality.
Designs and leads a full-stack Java/Angular platform that indexes unstructured medical data, enabling clinicians to build patient cohorts for cancer research using search, NLP, and AI.
Lead a fullstack team building a healthcare data platform for oncology research using Java/Spring, Angular, Elasticsearch, and AI tools to process unstructured medical data.
Designs high-speed VLSI circuits for next-gen CPU cores and caches using deep submicron FinFET processes, optimizing power, performance, and area while collaborating across teams.
Lead a team to implement and tape out high-performance ASIC/APU/dGPU designs for AI, gaming consoles, and automotive using RTL-to-GDS flows, PnR, timing closure, and physical verification.
Designs and verifies custom IC layouts for analog and digital circuits using Cadence Virtuoso and Mentor Calibre, including PLLs, DACs, and high-speed signaling blocks.
Designs digital IP blocks and SoCs for automotive systems, writing RTL in Verilog/VHDL and collaborating with verification, physical implementation, and validation teams.
Build and optimize electronic design automation tools and flows for semiconductor teams using Python and AI-assisted scripting to improve design efficiency and time-to-market.
Designs and optimizes advanced semiconductor IP and SoCs from RTL to GDSII, focusing on timing closure, power reduction, and physical verification for next-gen FPGAs.
Senior engineer who implements custom IP and SoC designs from RTL through GDSII, closing timing, optimizing power, and signing off on next-gen FPGA silicon using Synopsys/Cadence EDA tools.
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