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Architect and optimize EDA design environments for ASIC development, own digital and analog implementation flows, configure Cadence tools, refine physical design methodologies, automate workflows with scripting and…
Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. By driving down the cost and complexity of power delivery and…
Drive the product roadmap and GTM for Broadcom’s PCIe switch line, aligning AI/ML server architectures with market needs and collaborating with hyperscalers and OEMs.
Design and verify FPGA hardware using VHDL for radar, RF/EO DSP, and embedded systems; collaborate with systems engineers and verify designs with constrained-random tests.
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Modem Technologies Software General Summary: This individual leads, plans, synthesizes ambiguous or conflicting requirements and…
Leads cross-functional teams to develop automotive-grade ASICs, ensuring compliance with ISO 26262 and AEC-Q100 while managing schedules, budgets, and quality targets.
Design analog and mixed-signal high-voltage ICs for automotive systems like sensor interfaces and smart power devices, owning transistor-level circuits and guiding chip integration.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Define next-gen NIC and DPU chip architectures for NVIDIA’s networking unit, collaborating with GPU/CPU teams to optimize performance and debug full-chip correctness issues.
Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
As a Senior Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and…
Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.
Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a…
Lead the full lifecycle of NVIDIA’s next-gen switch ASICs, coordinating RTL design, verification, physical design, and post-silicon bring-up with cross-functional teams.
Program manager oversees NVIDIA GPU chip bring-up from power-on to production, coordinating wafer forecasts, allocations, and cross-functional teams to meet silicon schedules and mitigate risks.
Design AI/ML-driven automation for ASIC chip development, using GenAI, reinforcement learning, and neural networks to optimize power, performance, and area for NXP’s processors.
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Senior ASIC engineer designing on-chip interconnects and last-level caches for NVIDIA’s CPU and AI platforms, focusing on synthesis, timing closure, and performance optimization.
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