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Lead Engineer/ Staff – RISCV Subsystem RTL Design Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
Security RTL Design Engineer-Sr Lead/Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Senior IP Micro-architect (RTL) - Staff/Sr Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
Design verification engineer leading pre-silicon verification for complex SoCs, using UVM, SystemVerilog, and formal methods to ensure correctness of AI/ML accelerators, processors, and interconnects.
Designs and integrates ARM-based microcontroller subsystems for automotive applications, collaborating with cross-functional teams to deliver robust SoC solutions for modern vehicles.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Design-for-Test engineer responsible for inserting boundary scan, memory BIST, and scan logic into complex SoCs, running ATPG, and debugging silicon bring-up on ATE.
Working student role in DRAM design, assisting engineers with IC schematics, simulations, and verification for high-performance memory solutions in Munich.
This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that…
Design FPGA/ASIC digital systems for radar, electronic warfare, and communications using Verilog/VHDL, high-speed interfaces, and PCB tools while leading teams and collaborating across engineering and business functions.
Lead the physical design and implementation of high-performance processor chips from RTL to GDS in advanced nodes (5nm–2nm), managing global teams and sign-offs for timing, power, and DFM.
Lead the physical design and methodology for next-gen high-performance processor chips, managing RTL-to-GDS flows, timing, power, and sign-offs in advanced nodes (5nm–2nm) for server, 5G/6G, and networking applications.
Designs and optimizes high-performance processor chips from RTL to GDSII, leading physical design flows and automation for server, 5G/6G, and networking applications.
Builds and tests Jasper, a formal-verification tool for clock-domain-crossing issues in chip design, using C++ and Unix workflows.
Lead a team enhancing Jasper, a formal verification tool for clock domain crossing in hardware design, using C++ and Unix in a fast-paced R&D environment.
Senior engineer leading physical design and floorplanning for high-performance GPUs and SoCs at advanced technology nodes, optimizing power, performance, and area while mentoring peers and driving EDA/tool innovation.
Senior Solutions Engineer at F5 selling and demonstrating cybersecurity and cloud networking solutions to enterprise customers and partners, driving technical sales through consultative engagement and POCs.
Design and prototype next-gen AI hardware using FPGAs, focusing on SoC emulation, high-speed interfaces like PCIe/LPDDR, and bring-up for analog compute-in-memory chips.
Designs and implements automated test and debug features for AMD's complex processor and GPU chips, using scripting and AI/ML tools to improve chip reliability and performance.
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