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Principal Engineer designs and runs pre-silicon verification for DDR, HBM, and GDDR memory controller IP using SystemVerilog and UVM, with coverage-driven test suites and regression monitoring.
Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.
Principal PCIe logic engineer designs next-gen PCIe IP in SystemVerilog, collaborates with verification teams, and prototypes on FPGAs.
Senior embedded engineer designing and optimizing firmware/software for storage hardware, bridging hardware (FPGA) and software (Linux/RTOS) domains, and leading system integration from concept to production.
Senior Architect defines next-gen chip interconnects like NVLink, optimizing performance and power while driving ASIC design and cross-team implementation.
Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.
A working student in digital design will develop RTL-level technical solutions for microcontroller units (MCUs) and IPs, focusing on functional correctness via System Verilog and formal verification for automotive electronics.
Develop and maintain embedded C/C++ software for satellites, including flight systems, sensors, and actuators, while supporting mission operations and testing.
Designs and verifies high-speed USB 2.0 and eUSB2 chips, writing RTL code and debugging mixed-signal circuits for next-gen AI and IoT solutions.
Develop and test embedded cryptographic software for real-time systems in C/C++ and Rust, integrating firmware and hardware in an Agile environment with DoD Secret clearance.
Principal Logic Design Engineer Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our…
Design and verify next-gen System-on-Chip (SoC) components using Verilog/SystemVerilog, UVM, and C/C++ to ensure high-quality, industry-leading processor performance.
Design Verification Engineer at AMD builds and maintains tests to verify complex processor IP, debug failures, and collaborate with RTL and firmware teams to ensure high-quality silicon designs.
Verify next-gen x86 CPU cores by writing C++/SystemVerilog tests and checkers, debug RTL issues, and drive coverage closure in a hybrid Austin office.
Designs and enhances SystemVerilog/UVM testbenches to verify PCIe subsystem features, collaborating with architects and engineers to ensure robust RTL designs and memory subsystem performance.
Designs and validates test solutions for digital, analog, and photonic logic in AI-focused chip platforms, using DFT methodologies like ATPG and boundary scan to ensure silicon bring-up and product readiness.
Sr. Principal Digital Designer Location: Bangalore Time Type: Full time Job Description Role Summary We are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital…
Sr. Principal Embedded Systems Security Architect Location: Shanghai (Pudong) Time Type: Full time Job Description Shape the Security of Tomorrow's Connected World At NXP, security is at the heart of everything we…
2027 Internship- Hardware Engineer (FPGA) Location: Austin, TX Department: Internships Virtu is an industry-leading financial technology firm that operates both proprietary trading and client-facing businesses in the…
Designs and validates FPGA logic for networking hardware using Verilog/VHDL, vendor tools (Vivado/Quartus), and industry-standard flows to ensure first-pass success.
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