Tech jobs

Open 116d APACStaff H-1B sponsor history

Staff Engineer - Design Verification

Singapore

Design verification engineer at Ambiq Micro, Singapore, responsible for verifying low-power SoCs for IoT applications using SystemVerilog/UVM, ARM/RISC-V, and power-aware methodologies.

AI C++ I2c IoT Perl +6 skills

Ambiq Micro, Inc.

Open 131d North AmericaStaff H-1B sponsor history

Sr. Staff Engineer - Digital Design Verification

AI Automation C++ IoT Machine Learning +6 skills

Senior engineer who designs and runs verification tests for low-power System-on-Chip designs used in IoT and edge-AI products, using SystemVerilog, UVM, and C/C++.

180K – 250K $

CIS Secure

RF Engineer – Radio Systems / RF Hardware

Open 58d North America

C++ Cybersecurity Embedded Linux Embedded Software Embedded Systems +14 skills

RF Engineer leading the design, development, and integration of custom radio and RF hardware for national security missions, working across RF, FPGA, digital, and embedded systems at Aberdeen Proving Ground.

140K – 160K $

Cadence

AI Asic Automation FPGA GPU +5 skills

Principal Design Engineer

Open 57d EuropePrincipal

Ireland

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…

Cadence

AI Bash Perl Rtl SystemVerilog +2 skills

Sr Principal Design Engineer — Memory Modeling Portfolio

Open 57d APACPrincipal

China

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our…

Open 52d APACStaff H-1B sponsor history

Staff Field Applications Engineer

Taiwan

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

Embedded Systems FPGA Oscilloscope Pre-sales Proof of Concept +5 skills

Open 52d APACSenior H-1B sponsor history

Design Eng - Modeling

Philippines

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

AI Automation Bash C++ FPGA +8 skills

Open 52d APACStaff H-1B sponsor history

Senior Staff IP Design Engineer

Malaysia

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

FPGA Rtl SystemVerilog Verilog VHDL

Open 52d APACSenior H-1B sponsor history

Senior Soft IP Design Engineer

Malaysia

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

C++ FPGA I2c Perl Python +5 skills

Open 52d APACSenior H-1B sponsor history

Senior Design Verification Engineer

India

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

AI C++ Cryptography FPGA Generative AI +7 skills

Velaura AI, Inc.

Open 59d On-siteNorth America

Design Verification Engineer – CPU

C++ FPGA Prototyping Root Cause Analysis SystemVerilog +1 skills

Own pre-silicon verification of custom CPU units (fetch, decode, load-store, caches) by building SystemVerilog/UVM environments, developing instruction-level stimulus, running regressions, and supporting FPGA/emulation bring-up.

Velaura AI, Inc.

Open 59d On-siteNorth AmericaLead

Design Verification Engineer – AI Accelerator Lead

AI C++ LLM Neural Networks ONNX +5 skills

Own verification for custom AI acceleration units—translating microarchitecture into test/coverage plans, building SystemVerilog/UVM environments, developing GEMM/GEMV reference models, and supporting pre-silicon bring-up.

Lynk

Open 135d On-siteNorth AmericaFull-timeSenior H-1B sponsor history

Senior FPGA/AIE Engineer

C++ Ethernet Firmware FPGA IoT +6 skills

About Elveo Elveo is what happens when two pioneers in direct-to-device (D2D) communications join forces. Elveo brings together a combined 20 years of expertise to close the coverage gap for more than 50 mobile network…

Elveo

Open 54d On-siteNorth AmericaFull-timeSenior

Senior FPGA/AIE Engineer

C++ Ethernet Firmware FPGA IoT +6 skills

About Elveo Elveo is what happens when two pioneers in direct-to-device (D2D) communications join forces. Elveo brings together a combined 20 years of expertise to close the coverage gap for more than 50 mobile network…

Advanced Micro Devices, Inc

AI Firmware Git Perforce Rtl +3 skills

RTL Design & Validation Lead with DDR protocols exp

Open 60d APACLead

India

The Lead RTL Design & Validation Engineer will plan and execute the design and validation of DDR memory controller calibration solutions, including RTL logic and firmware routines. The role involves collaborating with cross-functional teams to ensure reliable memory initialization and performance across AMD's custom IP projects.

Li Auto

Bash Perl Python SystemVerilog Uvm

资深数字验证工程师

APAC

China

1. 负责复杂数字模块或子系统的验证方案制定、环境搭建与覆盖率提升，确保设计功能符合规格要求。 2. 基于 UVM/SV 构建验证平台，包括激励生成、参考模型、Scoreboard、Checker 等关键组件。 3. 主导模块级与子系统级的 Testplan 设计、随机和定向用例开发，推动覆盖率闭环。 4. 负责定位与分析仿真问题，跨团队协作（前端设计/架构/PD/DFT）推动问题根因定位与修复。 5. 支持 Gate-level…

General Dynamics Mission Systems, Inc

Open 59d On-siteNorth America

FPGA Engineer

Aurora CI/CD Corrective Action Ethernet FPGA +9 skills

FPGA design engineer on a cross-functional team building cost-sensitive secure products from architecture through production, primarily using VHDL/Verilog/SystemVerilog and Xilinx tools.

109K – 115K $

General Dynamics Mission Systems, Inc

Open 59d On-siteNorth AmericaSenior

Senior Advanced FPGA Engineer

Aurora CI/CD Corrective Action Ethernet FPGA +9 skills

Designs secure, cost-sensitive FPGA-based products from architecture to production, collaborating cross-functionally on defense systems with Zynq UltraScale+ MPSoC and Vivado tools.

160K – 173K $

Altera Corporation