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Qualcomm
7 views 2 months ago

ASIC Design Verification Engineer, up to Sr. Staff

Open 28d On-siteAPACStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Taiwan

Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Education MS/BS in EE (MS preferred) Experience 2–15 years ASIC verification experience…

Asic C++ Ethernet FPGA Networking +9 skills
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Istra
12 views 2 months ago

Senior VLSI Design Engineer

Open 53d On-siteSenior

The Istra Hardware team is a top-tier group focused on developing and refining the hardware capabilities within Istra's complex product. Our implementation process is end-to-end, covering all hardware development…

API C++ FPGA Python Tcl +2 skills
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Hewlett Packard Enterprise
11 views 2 months ago

Principal Hardware Engineer

Open 129d North AmericaPrincipal Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
United States

Principal Hardware Engineer designing and validating high-end routing platforms, collaborating with cross-functional teams on PCB design, signal integrity, power, and thermal considerations for mass production.

Automation Cloud Ethernet Firmware FPGA +14 skills
154K – 311K $
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NK Securities Research
8 views 2 months ago

Low Latency FPGA Developer

Open 135d APAC
India

The FPGA Developer will design, implement, and test high-performance RTL for low-latency high-frequency trading strategies. The role requires expertise in VHDL/Verilog, FPGA debugging tools, and collaboration with software teams to optimize trading system performance.

Automation Bash C++ Ethernet FPGA +10 skills
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SVENTL ASIA PACIFIC PTE. LTD.
7 views 2 months ago

Physical Design Engineer II

Open 108d APAC
Singapore

The Physical Design Engineer II is responsible for the end-to-end physical implementation of semiconductor designs, including netlist to GDSII, timing signoff, and floor planning. The role requires expertise in PnR tools like Synopsys ICC/ICC2 or Cadence Innovus and experience with advanced process nodes.

Tcl
SVENTL ASIA PACIFIC PTE. LTD.
8 views 2 months ago

Physical Design Engineer

Open 108d APAC
Singapore

The Physical Design Engineer is responsible for the end-to-end implementation of chip designs, from netlist to GDSII, including floor planning, timing signoff, and clock tree synthesis. The role requires expertise in industry-standard EDA tools like Synopsys ICC/ICC2 or Cadence Innovus and experience with advanced process nodes.

Tcl
SVENTL ASIA PACIFIC PTE. LTD.
8 views 2 months ago

Design Verification Engineer

Open 57d APAC
Singapore

The Design Verification Engineer will develop verification environments, test plans, and perform functional RTL testing at the IP and SoC levels. The role requires expertise in ASIC verification methodologies, SystemVerilog, and various communication protocols.

Asic Ethernet Perl Rtl SerDes +3 skills
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Apple Backed by Sequoia
7 views 2 months ago

ASIC Design Engineer — Pixel IP

Open 58d North America
United States

Front-end ASIC design engineer on Apple's Pixel IP team, writing RTL and micro-architectural specs for high-performance, low-power image/video processing pipelines in next-gen SoCs.

Asic C++ Perl Python Signal Processing +2 skills
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Apple Backed by Sequoia
6 views 2 months ago

ASIC Design Engineer — Pixel IP

Open 58d North America
United States

Front-end ASIC Design Engineer responsible for designing high-performance, power-efficient pixel processing engines for Apple's SoCs using RTL or high-level synthesis methodologies.

Asic FPGA Perl Python Signal Processing +2 skills
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Ambiq Micro, Inc.
2 views 2 months ago

Director - Silicon Validation

Open 115d North America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads post-silicon validation for ultra-low-power SoCs and edge AI chips, setting strategy, debugging silicon, and mentoring a global team to ensure first-pass success and rapid commercialization.

AI Analytics Automation Bluetooth C++ +6 skills
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Ambiq Micro, Inc.
5 views 2 months ago

Staff Validation Engineer - Power

Open 96d North AmericaStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads power validation and optimization for ultra-low-power SoCs, designing validation plans and automation tools while collaborating with cross-functional teams to ensure industry-leading energy efficiency.

AI Automation C++ Embedded Systems Firmware +4 skills
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Ambiq Micro, Inc.
6 views 2 months ago

Staff Validation Engineer - Wireless Radio Lead

Open 96d North AmericaStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Lead validation and optimization of ultra-low-power wireless radios (BLE, Bluetooth Classic, 802.15.4) for next-gen SoCs, defining test methods and automating RF characterization in a lab setting.

AI Automation Bluetooth C++ Embedded Systems +5 skills
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d-Matrix
12 views 2 months ago

Sr. Staff PCB Design Engineer

Open 58d HybridNorth AmericaStaff H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Leads PCB design for AI silicon hardware, focusing on high-complexity, high-layer-count boards (20+ layers) with ultra-high-speed interfaces (PCIe Gen5/6, CXL) and power delivery for AI accelerators. Owns layout methodology, automation, and tooling to scale hardware development.

AI API Automation Networking Pcb +5 skills
175K – 265K $
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broadcom
2 months ago

Physical Design Engineer

Open 57d North America
United States

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before…

AI Machine Learning PCIe Perl Tcl
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Tata Capital
2 views 2 months ago

Relationship Manager-Equipment Finance-Sales-Ahmedabad - Navrangpura-M1-M3*

Open 57d APACFull-time
India

Relationship Manager - Sales REPORTS TO (SOLID & MATRIX): Position Grade: Business Unit: SME Department: Sales Sub Function: EQF Location: Number of Positions: Single / Multiple Position Type: Full Time Job Purpose…

Risk Assessment Tcl
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Analog Devices
7 views 2 months ago

Staff Digital Design Engineer (FPGA)

Open 56d North AmericaFull-timeStaff Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Staff Digital Design Engineer responsible for FPGA/ASIC RTL design, board-level schematic capture, and system architecture for aerospace and defense applications (electronic warfare, radar, communications) using Verilog/VHDL, high-speed interfaces, and PCB tools.

AI Aurora Automation Business Development C++ +11 skills
135K – 202K $
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Marvell
10 views 2 months ago

Senior Staff Engineer, Physical Design

Open 56d North AmericaInternshipStaff
United States

Senior Staff Engineer performing physical design (place-and-route, static timing, physical verification) on next-generation high-performance processor/ASIC chips using EDA tools, with automation scripting in Shell, Python, and TCL.

AI Assembly Automation Bash ChatGPT +9 skills
112K – 166K $
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Cadence
10 views 2 months ago

Software Engineer II: Innovus R&D

Open 56d LATAM
Brazil

Software engineer developing and maintaining clock-tree synthesis algorithms in C++ and Tcl for the Innovus place-and-route EDA tool, including debugging, testing, and optimizing performance.

Agentic AI Automation Claude Code Cloud C++ +13 skills
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Cadence
6 views 2 months ago

Sr Principal Design Engineer — Memory Modeling Portfolio

Open 56d APACPrincipal
China

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our…

AI Bash Perl Rtl SystemVerilog +2 skills
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Lattice Semiconductor
8 views 2 months ago

Design Eng - Modeling

Open 51d APACSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Philippines

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…

AI Automation Bash C++ FPGA +8 skills
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