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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Senior engineer building and improving ASIC verification infrastructure, CI/CD flows, and AI-assisted debug tools for GPU development at NVIDIA.
ASIC Digital Verification Design, Principal Engineer - 18386
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, from AI infrastructure and cloud computing to autonomous systems and…
Principal Staff Silicon Design Engineer - DDR Verification
Lead verification of DDR5/LPDDR5 memory interfaces for AMD server chips using SystemVerilog, UVM, and C/C++; mentor engineers and align firmware/software with hardware requirements.
Design Verification Engineer
Design Verification Engineer at AMD builds and runs SystemVerilog/UVM testbenches to validate DDR5, LPDDR5, and DFI memory interfaces for server products, collaborating with hardware, firmware, and software teams.
Design Verification Engineer – Physical AI Compute
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Sr/Principal Design Verification (DV) Engineer
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced Design Verification Engineer to drive verification of complex next-generation AI/compute platforms.…
Staff Design Verification Engineer
Design Verification Engineer at Cerebras building and validating the world's largest AI chip, ensuring first-silicon success through SystemVerilog/UVM testbenches and cross-functional collaboration.
Sr FPGA Design Engineer
Design and verify FPGA-based hardware for Dolby’s cinema servers, audio processors, and HDR projection systems using VHDL/Verilog/SystemVerilog and advanced verification tools.
Microarchitect / RTL Design - Memory Subsystem
Design and implement memory controllers, hierarchies, and near-memory accelerators for AI-driven ASICs, optimizing bandwidth, latency, and power for ML workloads using SystemVerilog and AI-assisted flows.
Principal Design Verification Engineer – CPU Coherent Interconnect
Leads verification strategy for a high-performance CPU cache-coherent interconnect, defining test plans, assertions, and coverage to ensure protocol correctness and subsystem integration across multiple interfaces.
Principal Software Engineer - Compiler Development
Architect and optimize the next-generation SystemVerilog compiler for Xcelium, enabling faster verification of billion-gate AI and hyperscale chip designs using C++ and compiler theory.
Principal Electrical Engineer - FPGA Verification
Principal Electrical Engineer verifies FPGA-based radar designs using SystemVerilog, UVM, and industry simulators, ensuring functional correctness and coverage for control/signal-processing applications.
Principal Electrical Engineer - Digital Circuit Card Design
Designs high-speed digital circuit boards for military radar systems using CAD tools, power/signal integrity analysis, and embedded processors; collaborates on FPGA-based designs and hardware testing.
Senior Electrical Engineer - FPGA Verification
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.