Tech jobs

Renesas Electronics

NewBe an early applicant HybridNorth AmericaStaff

Staff Design Verification Engineer

Agile AI CAD IoT Iso 26262 +3 skills

Staff-level mixed-signal verification engineer at Renesas who verifies and models automotive power-management chips (PMICs, switching regulators, analog IP). Day to day: building UVM/RNM/AMS verification environments, running RTL and gate-level simulations, and debugging analog-digital interactions.

careers.nordicsemi.com

NewBe an early applicant EuropeLead

Senior SoC Design Lead

Finland

About the job In this role you will lead the team that takes Nordic's next-generation microcontroller and wireless SoCs from architecture and specification to tape-out and production. You own SoC-level design and…

Corrective Action Root Cause Analysis Rtl Stakeholder Management SystemVerilog +1 skills

NewBe an early applicant North AmericaSenior

RTL Design Engineer

RTL IP design engineer on AMD's Security IP (SECIP) team, doing block-level RTL design and subsystem integration of embedded microprocessor subsystems and hardware accelerators (security, crypto, compression, DMA, power management) across AMD SoCs. Core stack: Verilog/SystemVerilog, ASIC design flows, AXI/AMBA protocols, Python/Tcl scripting.

AI Asic Cryptography FPGA Perl +7 skills

a21467f2-5c74-46bf-bd5c-61cdb598d8b3:19000101_000001

NewBe an early applicant North AmericaStaff

Staff FPGA Engineer

Acceptance Criteria Ethernet FPGA Image Processing PCIe +6 skills

The Staff FPGA Engineer will lead the architecture, development, integration, and support of FPGA-based platforms used throughout Cytek's flow cytometry and imaging instrumentation portfolio. This role is…

NewBe an early applicant North America

CPU Core RTL Design Engineer

AI Python Rtl SystemVerilog Tcl +1 skills

Designs and implements RTL for next-generation high-performance CPU cores on AMD's central core RTL team, contributing pipeline logic and microarchitecture features across client, server, and AI platforms. Core technologies: Verilog/SystemVerilog, CPU microarchitecture, synthesis, timing closure, and pre/post-silicon debug.

IMC

NewBe an early applicant APAC

Hardware Engineer

Australia

Designs and deploys ultra-low-latency FPGA hardware for IMC's proprietary trading systems in Sydney, parsing market data and executing trades in nanoseconds. Day-to-day work spans VHDL/Verilog/SystemVerilog, FPGA toolchains like Vivado, and performance optimization alongside traders and software engineers.

C++ Ethernet FPGA Machine Learning Networking +5 skills

Apple

NewBe an early applicant UK

Design Verification Engineer - Power Management (Early Career or Experienced)

United Kingdom

Design Verification Engineer at Apple in Swindon verifying mixed-signal power management silicon pre-tape-out: building UVM testbenches, writing directed and constrained-random tests, running simulations, closing functional coverage, and automating verification flows through RTL freeze and tape-out. Core stack: SystemVerilog, UVM, Verilog/VHDL, logic simulators.

OOP Perl Python SystemVerilog Tcl +3 skills

skyspyai

NewBe an early applicant HybridEuropeFull-time

FPGA Engineer

Poland

Designs and optimizes high-performance FPGA/SoC solutions in VHDL/Verilog on Xilinx 7-Series/UltraScale and Zynq platforms, building DSP and RF/SDR signal-processing chains with Vivado. Full-time hybrid role in Warsaw at a dual-use startup building RF intelligence solutions for defense.

C++ Embedded Software Ethernet FPGA PCIe +6 skills

NewBe an early applicant North AmericaStaff

PLL Design/ Integration Sr Staff Engineer

Senior staff engineer on AMD's AECG Fabric team who architects, integrates, and characterizes PLLs and analog/mixed-signal blocks (VCOs, charge pumps, LDOs, phase interpolators) for FPGA/adaptive SoC products on cutting-edge process nodes — including layout review, lab bring-up, and system validation with Vivado.

AI FPGA SystemVerilog

Quantum Machines

Asic C++ Ethernet FPGA I2c +7 skills

FPGA Design Engineer

Open 67d On-siteMENA

Israel

FPGA Design Engineer owning the design and implementation of FPGA-based interfaces (PCIe, I2C, SPI, high-speed GT) on Xilinx UltraScale+ and Versal platforms for quantum computing control systems.

FuriosaAI

AI Bash PCIe Perl Python +3 skills

Hardware - Design Verification Engineer

Open 66d APAC

South Korea

Hardware Design Verification Engineer at FuriosaAI responsible for defining and implementing verification plans, building test benches, and debugging design failures using SystemVerilog/UVM methodologies and EDA tools.

FuriosaAI

AI Automation Bash Ethernet PCIe +4 skills

Hardware - Senior Design Verification Engineer

Open 66d APACSenior

South Korea

Designs and executes verification strategies for AI hardware, ensuring functional correctness and coverage of block/system-level designs using SystemVerilog/UVM and Python-based tools.

Fractile

Open 127d UK Licensed UK sponsor

Infrastructure Software Engineering – Platform & Build

United Kingdom

Infrastructure Platform Engineer at Fractile (an AI inference chip startup) in London: owns CI infrastructure end-to-end, scales a multi-language Bazel monorepo, builds observability/incident response, and manages infrastructure-as-code for hybrid cloud and on-prem. Core stack: Bazel, CI/CD, Terraform/OpenTofu/Pulumi, Prometheus/Grafana, Python/Go/Rust.

AI Automation Bazel CI/CD Cloud +16 skills

Modernize Chip Solutions

NewBe an early applicant On-siteAPAC

FPGA Engineer - ASIC Prototyping & Emulation

India

Ports ASIC RTL designs onto FPGA prototypes for pre-silicon emulation: refactoring clock/memory/analog blocks, running synthesis, place-and-route and timing closure in Xilinx Vivado, Intel Quartus or Synopsys ProtoCompiler, performing SpyGlass CDC sign-off, and bringing up boards with JTAG/logic analyzers while integrating PCIe, AXI, Ethernet and DDR interfaces.

Embedded Systems Ethernet FPGA I2c JTAG +8 skills

Google

NewBe an early applicant MENAJunior Licensed UK sponsor Licensed NL sponsor Denmark Fast-track company

Junior AI SoC Design Verification Engineer, Google Cloud

Israel

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…

AI Cloud GCP Networking SystemVerilog +2 skills

Jobgether

NewBe an early applicant RemoteNorth AmericaFull-time

SOC/IP Integration Engineer (eInfochips Inc)

AI Gdpr Process Improvement Rtl SystemVerilog +1 skills

Fully remote SOC/IP Integration Engineer for eInfochips (US) integrating SoC subsystems and first/third-party IP into chip architectures using Verilog/SystemVerilog. Day to day: RTL analysis, synthesis and timing constraints, design-quality checks (CDC, lint, RDC), and client communication, with occasional travel to a client office.

NewBe an early applicant EuropeStaff

Staff Silicon Design Engineer

Serbia

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…

AI C++ FPGA I2c JTAG +7 skills

Silicon Quantum Computing

AI CI/CD C++ FPGA Git +8 skills

Software Engineer, Control & Error Correction

Open 52d APACContract

Australia

Develops the realtime quantum control plane, including schedulers and compilers, to manage logical qubit operations and error correction. Works with Rust, C++, and Python on FPGA-based hardware with microsecond-level latency constraints.

Texas Instruments

Open 123d APAC Licensed UK sponsor

Digital Design Verification Engineer

India

We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation. Our current work is focused…

AI Automation Bash CI/CD FPGA +6 skills