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Develops and optimizes embedded software for silicon validation platforms, debugging pre- and post-silicon systems, and collaborating with hardware/firmware teams to resolve complex issues using C, AXI, PCIe, USB, and GEM protocols.
Designs high-speed digital and analog circuits for networking switches and routers, selects components, and ensures signal/power integrity for interfaces like Ethernet and PCIe.
Develops a new automation tool for silicon CAD (chassis automation) to generate RTL, register definitions, and verification collateral from user requirements, collaborating with RTL, verification, and SoC teams using Python, structured schemas, and CI/CD pipelines.
Lead and manage end-to-end silicon validation activities spanning pre-silicon correlation, post-silicon functional validation, system validation, bench characterization, wafer probe evaluation, and ATE test…
Member of the Technical Staff - Systems Department: Engineering Location: North America Remote / San Francisco, CA Employment Type: FullTime Member of the Technical Staff, Systems Location: North America Remote / San…
Designs high-performance PCIe Gen6/Gen7 switch ASIC IP using SystemVerilog, focusing on RTL implementation, timing closure, and architecture for next-gen connectivity solutions.
Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.
Principal PCIe logic engineer designs next-gen PCIe IP in SystemVerilog, collaborates with verification teams, and prototypes on FPGAs.
Senior embedded engineer designing and optimizing firmware/software for storage hardware, bridging hardware (FPGA) and software (Linux/RTOS) domains, and leading system integration from concept to production.
Develop low-level diagnostics and system software for an AI inference platform, including firmware, drivers, and Linux kernel modules, while collaborating with hardware teams on bring-up and optimization.
Act as the main technical interface supporting customer design-in for NXP automotive processors, guiding hardware, software, and system architecture. You will drive technical engagement using Arm multi-core platforms, Linux, RTOS, and embedded high-speed interfaces.
Designs and oversees AI factory infrastructure architecture, defining system management protocols (Redfish, PLDM, etc.) and hardware-software interfaces for GPU/DPU/CPU systems, ensuring seamless provisioning, power management, and secure operation across data center components.
Architect next-gen host management software and firmware for NVIDIA networking platforms, defining cross-domain flows, telemetry, recovery, and power control across host, BMC, and device layers.
Principal validation engineer designs and runs post-silicon tests for SSD chipsets, ports bare-metal firmware, and analyzes power/performance to ensure storage SoC functionality.
Senior engineer who troubleshoots and supports customers integrating Marvell’s Ethernet switching chips, from pre-sale through production, using C/C++, Linux, and networking protocols.
Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Develops and optimizes embedded Linux BSPs, device drivers, and kernel configurations for Qualcomm QCS-based hardware, focusing on board bring-up, hardware-software integration, and debugging boot/peripheral issues.
Designs and verifies high-speed USB 2.0 and eUSB2 chips, writing RTL code and debugging mixed-signal circuits for next-gen AI and IoT solutions.
Develop and test embedded cryptographic software for real-time systems in C/C++ and Rust, integrating firmware and hardware in an Agile environment with DoD Secret clearance.
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