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Microchip Technology Backed by Sequoia
6 views 3 months ago

Technical Staff Engineer - Design

Open 81d APAC, CIS, North AmericaStaff Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.

Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.

Automation Big Data Jira JTAG Machine Learning +7 skills
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Microchip Technology Backed by Sequoia
12 views 3 months ago

Principal Engineer - Analog Design

Open 81d North AmericaPrincipal Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.
Canada

Designs and validates high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, filters) for multi-GHz timing products using Cadence tools and Verilog-A modeling.

Accessibility Automation Perl Python Tcl +1 skills
107K – 157K $
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VinFast
8 views 3 months ago

CAE Modeling, Morphing & Integration Engineer

Open 52d APAC
Vietnam

Builds, maintains, and integrates finite element (FE) CAE models for VinFast vehicle development — handling geometry cleanup, meshing, morphing, and model assembly to support Crash, Durability, NVH, Safety, and Optimization teams. Core tools include HyperMesh, ANSA, LS-DYNA, Nastran, and Abaqus.

Assembly Automation CAD PLM Python +3 skills
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Qualcomm
6 views 3 months ago

Senior Design Verification Engineer- Haifa, Hod Hasharon, Ramat Gan

Open 40d On-siteMENASenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm’s Peripheral IP organization is looking for a Senior Design Verification Engineer to develop…

Asic Automation Bash CAD Linux +9 skills
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Qualcomm
4 views 3 months ago

Infra Design Verification Sr Engineer

Open 27d On-siteAPACSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible…

Automation Ethernet FPGA PCIe Perl +5 skills
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ByteDance
4 views 3 months ago

芯片定制IP设计工程师（芯片平台） - 芯片研发

APACJunior
China

团队介绍：字节芯片研发团队目前工作主要集中在芯片设计环节，主要围绕字节自身业务展开芯片探索，为字节多项业务的专用场景定制硬件优化，设计多款基于先进半导体工艺的云端复杂芯片，以期提升性能、降低成本。早期若干芯片项目已经进入到量产部署阶段，有多次一版成功的投片经历，所用工艺包含多个主流的先进工艺节点。与基础设施各团队之间工作的整体协同，能更容易和更好地发挥芯片研发的价值。…

Bash Tcl
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Western Digital Backed by Sequoia
10 views 3 months ago

Senior Engineer, Systems Design Engineering

Open 82d APACSenior Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
Malaysia

Designs and troubleshoots hard-disk-drive systems, analyzing failures in electromechanical, firmware, and media components to improve yield and quality.

C++ Firmware FMEA MATLAB Minitab +4 skills
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ChipAgents
5 views 3 months ago

Applications Engineer

Open 80d On-siteNorth America
United States

Applications Engineer at ChipAgents guides enterprise customers through AI-driven chip design and verification workflows, integrating tools like Synopsys VCS and Cadence Xcelium to accelerate RTL development and verification.

Agentic AI AI Automation Bash Cloud +10 skills
130K – 350K $
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Rambus
10 views 3 months ago

SMTS Layout Design

Open 82d APAC H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Designs and verifies chip-level layout for high-performance memory-interface chips using Cadence Virtuoso and Calibre in 22nm–7nm nodes.

AI Cadence Virtuoso Perl Tcl
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Rambus
7 views 3 months ago

Design Verification Principal Engineer

Open 82d North AmericaFull-timePrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Engineer designs and runs pre-silicon verification for DDR, HBM, and GDDR memory controller IP using SystemVerilog and UVM, with coverage-driven test suites and regression monitoring.

AI Python Rtl Tcl Verilog
127K – 237K $
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Rambus
8 views 3 months ago

Lead MTS Design Verification Engineer - PCIe Controller products

Open 82d EuropeFull-timeLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
Bulgaria

Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.

AI Express.js PCIe Python Rtl +4 skills
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agad-technology
10 views 3 months ago

Senior FPGA Engineer (VHDL/Verilog)

Open 82d EuropeSenior
Belgium

Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.

Automation Ethernet FPGA Jenkins Linux +8 skills
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NVIDIA Backed by SequoiaBacked by SoftBank Vision Fund
8 views 3 months ago

CAD Developer, IR, Timing and Physical Design Optimization

Open 82d APAC
China

Develop and optimize C++ algorithms for IR drop, timing, and physical design to improve chip performance and power efficiency in advanced VLSI flows.

CAD C++ Distributed Computing Multithreading Perl +2 skills
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Altera Corporation
12 views 3 months ago

FPGA Compiler (Placer) Engineer

Open 82d North America
Canada

Develop and optimize FPGA placement algorithms to improve timing, power efficiency, and design quality within Altera’s compiler toolchain.

AI Automation CAD Cloud C++ +4 skills
129 – 187 CAD
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Positron AI
11 views 3 months ago

ASIC Design Engineer

Open 54d North America

Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…

AI Asic Automation Machine Learning PCIe +5 skills
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onsemi
14 views 3 months ago

Senior Design Verification Engineer

Open 84d APACSenior
India

Leads digital IC verification for mixed-signal IP (DACs, ADCs, PLLs) in automotive/industrial/medical products, designing SystemVerilog/UVM environments, debugging RTL, and improving verification methodologies.

Embedded Software Python Signal Processing Tcl Uvm +1 skills
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hctz.fa.us2.oraclecloud.com/CX
4 views 3 months ago

Senior Design Verification Engineer

APACSenior
India

We are looking to expand our team with a Senior Digital IC Verification Engineer . You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will…

Embedded Software Python Signal Processing Tcl Uvm +1 skills
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Positron AI
9 views 3 months ago

ASIC Design Verification Engineer

Open 54d HybridNorth America
United States

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for developing and…

AI Asic FPGA Machine Learning Perl +5 skills
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Advanced Micro Devices, Inc
19 views 3 months ago

2027 Term 1 Internship – IC Design Exploration Intern

Open 88d APACInternshipIntern
Singapore

An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.

AI Automation Bash Cadence Virtuoso Cloud +15 skills
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Microchip Technology Backed by Sequoia
7 views 3 months ago

Technical Staff Engineer-Design

Open 85d APAC, EuropeStaff Ireland permit employer — This employer was issued Irish employment permits this year or in the two years before, per the Department of Enterprise, Tourism and Employment. The permits belong to the employer and are not a commitment to sponsor this role.

Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.

Asic Bluetooth Ethernet FPGA I2c +6 skills
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