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The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
The ASIC Design Engineer 2 will work on high-speed networking chips, handling tasks from functional specification to final netlist. The role involves RTL coding, timing closure, and debugging using System Verilog and state-of-the-art EDA tools.
The ASIC Design Engineer 2 will contribute to the development of high-speed networking chips by performing RTL coding, micro-architecture specification, and timing closure. This role involves working with state-of-the-art EDA tools to design and debug complex silicon modules for routers and switches.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Profile Role Title Lead Design Engineer, SoC / Subsystem / IP Design Experience 4to 18 years…
The RTL Design Team Lead will manage a hardware engineering team while remaining hands-on with complex FPGA and ASIC design for 5G and satellite communications. The role involves technical leadership, RTL development, and cross-functional collaboration to deliver high-performance signal-processing IP.
Senior FPGA Engineer leading RTL design and FPGA development for spaceborne radar systems, working with Verilog/VHDL, synthesis, place-and-route, and timing analysis on FPGA/SoC platforms.
As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our…
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Leads the design and implementation of high-performance digital circuits for AI connectivity chips, using PCIe, CXL, Ethernet, and DDR protocols, from architecture to silicon bring-up.
Designs and implements digital blocks for semiconductor chips powering AI infrastructure, using Verilog/SystemVerilog and RTL coding principles with industry EDA tools.
Leads a team to verify complex semiconductor designs for AI infrastructure, focusing on PCIe, CXL, and UVM methodologies to ensure silicon success.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Design Verification Intern at Astera Labs working on silicon engineering for high-performance compute and networking standards using RTL design languages like Verilog and SystemVerilog.
Backend engineer responsible for synthesis (RTL to gate-level), DFT tasks (scan insertion, ATPG, MBIST), and STA/timing closure on large-scale chips at 28nm or below, collaborating with RTL and PnR teams.
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