Tech jobs

Optiverus

New EuropeInternshipJunior

Graduate FPGA Engineer (2027 Start)

Netherlands

Graduate FPGA Engineer (2027 start) at trading firm Optiver in Amsterdam: after a paid Global Academy training program, you design low-latency, highly parallel FPGA hardware for network infrastructure and trading systems with nanosecond response times. Core stack: VHDL/Verilog/SystemVerilog and FPGA/ASIC design.

AI FPGA Networking SystemVerilog Verilog +1 skills

Integrated Core Systems

New North AmericaContractStaff

Business Development Partner: Control & Embedded Systems

Automation C++ Embedded Systems FPGA Java +11 skills

Commission-only independent-contractor sales partner for Integrated Core Systems' ICore Blocks, a block-diagram simulator and code generator for control, robotics and ML systems. You lever an existing industry network to open doors and close license and SDK integration deals ($30k-$500k), fully remote worldwide.

SK Hynix Memory Solution

New North AmericaInternshipIntern

ASIC Design Intern

AI Cloud Firmware Linux Machine Learning +7 skills

Six-month, full-time internship in San Jose on SK hynix's SoC design team building SSD controllers for enterprise and AI data centers. The intern writes RTL in Verilog/SystemVerilog for IP modules and documents/collaborates with verification, silicon validation, and firmware teams.

35 – 45 $ / hr

Astera Labs

Open 100d MENAPrincipal H-1B sponsor history Canada LMIA employer

Staff / Principal ASIC Design Engineer

Israel

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

AI Asic Automation Ethernet PCIe +5 skills

waymo

Open 133d HybridNorth AmericaFull-time Licensed UK sponsor H-1B sponsor history

ASIC Design Verification Engineer

AI Automation C++ Ethernet Generative AI +6 skills

Designs and verifies custom silicon for autonomous vehicles, using UVM/SystemVerilog to validate hardware functionality and performance in a hybrid work environment.

175K – 215K $

waymo

Open 80d HybridNorth AmericaFull-timeStaff Licensed UK sponsor H-1B sponsor history

Staff SoC Design Engineer

AI Automation C++ Firmware Machine Learning +4 skills

Design next-gen SoCs for autonomous vehicles, defining hardware specs and RTL while optimizing performance, power, and latency for Waymo’s compute platform.

251K – 310K $

waymo

New North AmericaFull-timeStaff Licensed UK sponsor H-1B sponsor history

Staff ML Accelerator Architect

Machine Learning SystemVerilog

Staff-level architect on Waymo's Compute Team who maps autonomous-driving ML inference workloads onto custom accelerator hardware, builds performance modeling tools, and co-designs HW/SW solutions with compiler and model teams. Core focus: ML accelerator/microarchitecture design for the Waymo Driver's compute platform.

251K – 310K $

Apple

RFIC Design Engineer

New North America

Cadence Virtuoso Cmos Firmware MATLAB Rtl +1 skills

Designs RF/analog building blocks (TX, RX, PLL-LOGen) for Apple's wireless connectivity SoCs on the Wireless Radio team in Irvine — from architecture and transistor-level design in Cadence Virtuoso through simulation, extraction, silicon bring-up, and production correlation.

Apple

Design Verification Engineer

New North America

Assembly C++ Python Rtl SystemVerilog +2 skills

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy…

Apple

RFIC Design Engineer

Open 126d North America

Cadence Virtuoso MATLAB Rtl SystemVerilog

Designs analog, mixed-signal, and RF circuit blocks (LNAs, PAs, PLL/VCO, mixers, baseband filters, data converters) for radio transceivers integrated into Apple's wireless SoCs, covering architecture through silicon characterization and debugging, using Cadence Virtuoso, Spectre RF, Matlab, and EM simulation tools.

Delos Data Inc

New RemoteNorth AmericaFull-time

RTL Design Engineer

AI Claude Code Machine Learning Networking Python +5 skills

Senior RTL Design Engineer at a startup building hardware infrastructure for large-scale AI data center clusters. The role translates architectural specs into scalable microarchitectures and production-ready Verilog/SystemVerilog RTL, covering linting, CDC, simulation, timing closure, and collaboration with verification and physical design teams.

160K – 240K $

OPSWAT

New North AmericaContract H-1B sponsor history

Engineering Manager - FPGA & Hardware - Enforced Security

Agentic AI AI Assembly Cybersecurity DLP +11 skills

Leads and builds OPSWAT's FPGA engineering team for MetaDefender NetWall, hardware-enforced one-way security gateways for critical infrastructure and government. Owns silicon/board selection, RTL architecture, UVM verification, timing closure, and PCIe/TCP/TLS protocol termination in gateware toward 100 Gbps and NCDSMO certification.

AFRY

New Europe Licensed NL sponsor Canada LMIA employer

FPGA-Designer till Försvarsindustrin

Sweden

AFRY is hiring an FPGA designer to work with defense-industry clients in Linköping, Sweden: designing (and possibly verifying) FPGAs for safety-critical defense and security products, plus system work, requirements, testing and delivery. Core stack: VHDL (plus Verilog/SystemVerilog), multi-clock design and test frameworks like UVM; Swedish citizenship and security clearance required.

FPGA SystemVerilog Uvm Verilog VHDL

Microtech Global Ltd

Design Verification Engineer

New HybridUKFull-time

Design Patterns OOP Perl Ruby SystemVerilog +2 skills

Design Verification Engineer (all levels) verifying complex mixed-signal ICs: defining verification plans, leading/coaching verification engineers, and building reusable SystemVerilog/UVM testbenches with metric-driven coverage. Hybrid role (two office days per week) in Newbury or Edinburgh, paying £50,000–£90,000.

50K – 90K £

Design Verification Engineer (EDI)

Design Patterns OOP Perl Ruby SystemVerilog +2 skills

Design Verification Engineer at Cirrus Logic (Edinburgh or Newbury, UK) verifying complex mixed-signal ICs: defining verification plans, building reusable UVM testbenches, analyzing coverage, and coaching verification teams. Core tech: SystemVerilog/SVA, UVM/OVM, RTL/gate-level debugging, with scripting and power-aware verification as pluses.

Design Verification Engineer (NWB)

Design Patterns OOP Perl Ruby SystemVerilog +2 skills

Cirrus Logic is hiring Design Verification Engineers (all levels) in Newbury or Edinburgh, UK (hybrid, 2+ days in office) to verify complex mixed-signal ICs: defining verification plans, building reusable testbenches, and leading/coaching verification engineers. Core stack: SystemVerilog/SVA, UVM/OVM/e/VMM, metric- and coverage-driven verification.

Digital Design Engineer (TR-NWB)

Automation Cmos I2c MATLAB Microcontrollers +3 skills

Cirrus Logic is hiring a Digital IC Design Engineer in Newbury, UK to design and develop digital circuit architectures and SoCs for consumer mixed-signal products — taking blocks from concept through RTL design, verification, and synthesis to production, and mentoring junior engineers.

Design Verification Manager

Design Patterns OOP Perl Python Ruby +3 skills

Leads the digital verification team at Cirrus Logic's Newbury site, guiding engineers through full mixed-signal IC verification: shaping strategy, mentoring, and hands-on debugging using SystemVerilog, SVA, and UVM/OVM-class testbench methodologies.

New HybridNorth America H-1B sponsor history

Analog Design Engineer

Cmos MATLAB Signal Processing Simulink SystemVerilog +1 skills

Analog Design Engineer at Cirrus Logic in Austin, TX (hybrid): designs analog/mixed-signal IC blocks — data converters, power management, amplifiers — in advanced CMOS, owning architecture, transistor-level design, simulation (Spectre, Matlab, Verilog-A), layout closure, and silicon bring-up through production.