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Physical Design Engineer
You drive physical implementation and sign-off of critical blocks for AI and high-performance computing silicon. You own designs from RTL to GDSII, optimize floorplans, placement, clocking, routing, timing, power, and…
PLM Software Developer
Develop and customize PLM software integrations with Siemens Teamcenter and Windchill, collaborating with cross-functional teams to translate requirements into technical solutions.
Principal Digital Design Engineer
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.
Senior DevOps Developer (PDSW scrum) [585]
Build and run hybrid-cloud and on-premises infrastructure for quantum computing services, automating CI/CD pipelines and monitoring high-performance systems.
IC Senior/ Staff Physical Design Engineer (IC Backend)
Senior/Staff Physical Design Engineer leading backend chip development from netlist to GDSII, including floorplanning, P&R, STA, and tapeout prep.
AI Chip Backend Design Engineer (5nm+)
Design and optimize AI chip backend tools and flows for 5nm+ process nodes, including timing analysis, physical design, and EDA automation.
Senior IC Backend Implementation Engineer
Designs and optimizes integrated circuit back-end flows for IoT SoCs, focusing on floorplanning, clock-tree synthesis, and power efficiency using scripting (Python/TCL/Perl).
SOC Frontend Integration Engineer
Integrate RTL blocks into top-level SoC designs using Verilog/SystemVerilog, run lint/CDC checks, and hand off to downstream teams for physical design and verification.
Liberlo recrute : Développeur Backend PHP/Laravel confirmé (H/F)
Build and maintain secure, high-performance backend APIs and services using PHP/Laravel, collaborating with product and frontend teams to evolve a robust SaaS product.
Staff Engineer, Physical Design
Lead block- and subsystem-level physical design closure for complex SoCs, focusing on timing, congestion, power integrity, and clocking methodologies using tools like Synopsys ICC2 and Cadence Innovus.
Experience IT Systems Administrator
Maintains and improves IT infrastructure, including networks, servers, and cloud services, while providing 24/7 support and troubleshooting for internal systems and user needs.
Senior Software Engineer, DevOps and Security Solutions
Build and maintain core hardware-security software and automation tooling in C++/Python, improving performance and reliability for semiconductor design workflows.
AI and Design Automation Engineer
Build AI-driven automation for semiconductor package design, optimizing routing, placement, and verification to accelerate next-gen chip packaging workflows.
AI Application Developer
QA specialist testing FortiOS, Fortinet’s cybersecurity OS, using manual and automated methods to validate features and document defects.
Python Developer
Build Python automation tools to streamline semiconductor engineering workflows and improve efficiency for global teams.
FPGA Engineer
Design and maintain FPGA firmware for aerospace systems, including SoC integration, signal processing, and radiation-hardened embedded software for space electronics.
CPU Physical Design Engineer
Designs and optimizes CPU physical layouts for Google’s custom silicon, focusing on synthesis, place-and-route, timing closure, and power efficiency.
Design Verification Engineer
Verify ASIC designs by writing SystemVerilog testbenches, running simulations, and debugging with DVE/Verdi to ensure next-gen Cisco chips meet spec.
Technical Program Manager, PDK/IP
Owns PDK/IP infrastructure and vendor engagement for Cisco’s hardware platforms, coordinating ASIC flows, foundry processes, and cross-functional teams to deliver silicon tape-outs on schedule.