Velaura AI, Inc.
Open positions
SoC Design Verification Lead
You will own the SoC verification strategy, plan, architecture, and execution. You will lead verification engineers, coordinate system-level verification areas, drive coverage closure and tape-out readiness, report…
SoC Design Verification Engineer
You will plan and execute system-level SoC verification, build simulation environments, and verify boot, security, clock, reset, low-power, IO, and memory behavior. You will run CDC and RDC analysis, assess…
Senior Engineer CAD Pre-Silicon Front End
You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT…
Design Verification Engineer – CPU
Own pre-silicon verification of custom CPU units (fetch, decode, load-store, caches) by building SystemVerilog/UVM environments, developing instruction-level stimulus, running regressions, and supporting FPGA/emulation bring-up.
Design Verification Engineer – AI Accelerator Lead
Own verification for custom AI acceleration units—translating microarchitecture into test/coverage plans, building SystemVerilog/UVM environments, developing GEMM/GEMV reference models, and supporting pre-silicon bring-up.
Senior Design Verification Engineer – Physical AI Compute
Design and execute verification plans for a Physical AI SoC using SystemVerilog/UVM, C/C++, assertions, and emulation to validate compute engines, memory, and interconnects.
Principal AI SoC Runtime Software Architect
Own the software architecture for a heterogeneous AI SoC and define the end-to-end runtime across sensor ingest, preprocessing, AI inference, postprocessing, and application delivery. Coordinate workloads and data…
RTL Designer – Physical AI Compute
Design and optimize RTL for AI-focused System-on-Chip components, focusing on performance, power, and area while collaborating on verification and physical design.
Performance Modeling Architect – AI Systems
Designs and builds system-level performance models and simulations for AI workloads and hardware, analyzing bottlenecks to guide AI compute architecture decisions.
Design Verification Engineer – Physical AI Compute
Develop and execute verification strategies for complex SoC components and systems, building SystemVerilog and UVM environments, verifying hardware-software interactions, analyzing performance and real-time behavior,…
Security Architect
Design and own the security architecture for a Physical AI SoC, including hardware roots of trust, secure boot, and key management to protect AI workloads and sensitive assets.
Power Management Architect, Physical AI SoC
Architects power management for an AI-focused SoC, defining power domains, DVFS, and thermal strategies to optimize performance and energy efficiency in silicon.
Functional Safety Architect
Architect functional safety for a Physical AI SoC, defining safety goals, mechanisms, and fault-handling strategies across silicon and embedded platforms.
AI Systems Architect
Designs and optimizes AI model architectures for specialized hardware, mapping model requirements to efficient silicon implementations and improving performance and scalability.
Director of Finance
Lead financial strategy, planning, budgeting, forecasting, accounting operations, reporting, cash flow, capital allocation, treasury functions, audits, tax filings, regulatory reporting, financial systems, growth…
DFT Engineer Architect Manager Senior Manager
Lead DFT architecture and implementation for AI ASIC/SoC designs, including scan, BIST, ATPG, and post-silicon debug, while mentoring engineers and improving test flows.