Experienced Verification Engineer - System IP
Posted 8
views
Description
- Contribution to System IP microarchitecture specification and design
- Contribution in SystemVerilog, C and C++ to verification, modelling and debug
- Proposal and prototyping of new ways and methodologies to reach goals more efficiently
- Ownership and development of verification plans and environments
- Collaboration with engineers across design, performance modelling, validation, and implementation to meet functional requirements, performance, power and area goals
- Master’s degree in Electrical Engineering or Computer Engineering strongly preferred
- Bachelor's degree along with related experience
- Experience in object oriented software development (C++ or SystemVerilog preferred)
- Interest in and theoretical knowledge of digital circuits, FPGAs, embedded software (C)
- Enthusiasm and curiosity to learn new things and ways
- Post-degree work experience
- Exposure to all stages of the product development cycle: initial concept, specification, implementation and testing, documentation, release and support
- Experience with block level RTL design and verification of non-trivial ASIC or FPGA developments; SystemVerilog preferred
- Scripting skills, e.g. Linux, Bash, Python
- Ability to travel occasionally for training and customer meetings
- Proficiency in both written and oral English
- Competitive salary in the range of HUF 21,250,000 - HUF 28,750,000 per year
- Visa sponsorship for employee only, excluding spouse/dependants
- Hybrid working environment supporting high performance and personal wellbeing
- Benefits supporting physical and mental wellbeing
- Benefits supporting work and life success
- Financial rewards beyond competitive salary
- Professional and personal development opportunities
- Supportive community environment