FPGA Design Engineeer

Responsibility

Development of FPGA system using FPGA chassis that support software acceleration related system

solutions. Candidate should have good understanding of periperal interconnects (eg PCIe), network

protocols, memory systems. Candidate will be also required to understand customer system level

requirements and work with software and firmware teams to design and implement complete system level

solutions which includes both soft IP as well as FPGA hard IP blocks.

Responsibilities include architecture development, design, simulation, and hardware validation, and

documentation of scalable and configurable IP cores.

Requirements

Understanding of Verilog/VHDL RTL design and simulation, hardware debug and bring-up

 Knowledge of microelectronics circuit and functionality to FPGA/ASIC products

 Well-versed with FPGA/ASIC design flow

 Understanding of high-speed logic design, timing and power optimization design techniques

 Expertise/knowledge of digital communication and networking standards

 Proven track record of successfully architecting and implementing major functional blocks in

one or more chips in compute, networking and storage areas.

 Expertise in one or more connectivity protocols including PCI Express, 10/40/100Gbit Ethernet

as well as memory interfaces such as DDR3/4

All your information will be kept confidential according to EEO guidelines.