FPGA RTL Designer
Posted Updated
Description
Experience Required:
- 4 to 10 years of relevant FPGA Design/Verification experience.
- Candidates with strong hands-on FPGA development and debugging experience will be preferred.
Educational Qualification:
- B.E./B.Tech or M.E./M.Tech in Electronics, Electronics & Communication, Electrical Engineering, VLSI Design, Embedded Systems, or related disciplines.
- Candidates from reputed engineering colleges and universities will be preferred.
FPGA Design Engineer Requirements
Digital Design Fundamentals
- Strong understanding of:
- Combinational and Sequential Logic
- Finite State Machines (FSM)
- Clock Domain Crossing (CDC)
- Synchronization Techniques
- Timing Analysis and Timing Closure
- Setup Time, Hold Time, Recovery/Removal Checks
- Slack Analysis and Timing Violation Debugging
HDL Development
- Strong Verilog/SystemVerilog and/or VHDL coding skills
- RTL Design, Simulation, Synthesis, and FPGA Implementation
Protocol Knowledge
- UART, SPI, I2C
- Ethernet
- PCIe
- Added advantage:
- JESD204B/JESD204C
- 10G/25G/40G/100G Ethernet MAC
- MACsec
- IPsec
- High-speed serial interfaces
DSP and Signal Processing
- Hands-on implementation of DSP algorithms in FPGA
- Experience with filtering, FFT, digital signal processing pipelines, and optimization techniques is highly preferred
FPGA Platforms
- Practical experience with FPGA boards from:
- Xilinx/AMD
- Microchip (Microsemi)
- Intel (Altera)
Debug and Validation
- FPGA bring-up and board-level debugging
- ChipScope/ILA/SignalTap or equivalent debugging tools
- Hardware validation and troubleshooting
- Experience using Oscilloscopes, Logic Analyzers, and Lab Equipment
FPGA Tools
- Experience with any of the following tools:
- Vivado
- Libero SoC
- Quartus Prime
- ModelSim/QuestaSim
- Experience with additional FPGA design tools will be an added advantage
"RTL design for low power implementations", "Knowledge in Partial reconfiguration" also in the list as an added advantage.