Principal Digital Design Engineer

Job Purpose:

Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader driving innovation in gallium nitride (GaN) and high-voltage silicon carbide (SiC) technologies. Our products enable faster, more efficient power delivery across AI data centers, high-performance computing, energy and grid infrastructure, and industrial electrification.

With more than 30 years of combined expertise in wide bandgap technologies, GaNFast™ power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC™ high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications.

We are seeking a Principal Digital Design Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth, innovative environment, contributing directly to technologies that are shaping the future of power electronics.

Key Responsibilities and Duties:

• Design and implement digital blocks for ASICs using Verilog/SystemVerilog and standard ASIC design flows.

• Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries.

• Develop and maintain UVM/SystemVerilog testbenches, including functional coverage models, assertions (SVA), and constrained-random stimulus.

• Own coverage closure: analyze code and functional coverage, find gaps, and drive improvements in existing verification suites.

• Apply formal verification where it fits, such as property checking, connectivity, and register and FSM verification.

• Build mixed-signal verification using real-number modeling or AMS co-simulation to verify digital-analog interactions.

• Support ASIC tape-out activities, including synthesis, static timing analysis, and design signoff.

• After silicon returns from the foundry, focus on developing FPGA-based test builds (using Xilinx tools) to validate and characterize fabricated PMIC silicon.

• Interface and integrate digital control logic with analog/mixed-signal blocks commonly found in power management applications.

• Own digital architecture specs from product requirements through tape-out.

• Lead design and verification reviews, and follow coding, verification, and methodology standards set by the team.

• Mentor junior engineers and provide technical direction across multiple projects.

• Lead post-silicon debug and root-cause analysis, and feed silicon learnings back into design and verification.

• Evaluate and improve design and verification flows and tools to increase team productivity and reuse.

• Write and maintain automation scripts for regression testing, build flows, and hardware validation.

• Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers to ensure robust and reliable PMIC design.

Knowledge, Skills, Abilities, and Other Characteristics (KSAO’s)

• Digital design principles: synchronous/asynchronous design, FSMs, clock-domain crossing, reset strategies, and low-power techniques.

• ASIC flow from start to finish: RTL, synthesis, STA, DFT, equivalence checking, place and route handoff, and signoff.

• Verification methodology: SVA, functional and code coverage, constrained-random testing, and formal verification concepts.

• PMIC and power electronics basics: DC-DC converter control, sequencing, protection and fault handling, trimming, and how digital logic interacts with analog blocks.

• Mixed-signal modeling and co-simulation concepts.

• Serial protocols: I²C, SPI, PMBus/SMBus.

• Standard cell libraries, timing constraints (SDC), and process corner/variation effects.

• Post-silicon validation and ATE test concepts.

• Hands-on with Cadence tools: Xcelium, Genus, Conformal, Modus, Tempus/Innovus, Voltus, etc.

• Xilinx Vivado and FPGA prototyping for silicon validation.

• Scripting and automation in Python, Tcl, Bash, Make, etc.

• Lab skills: oscilloscopes, logic analyzers, protocol analyzers, and bench equipment for silicon debug.

• Turning product-level requirements into digital architecture.

• Root-causing complex failures across pre-silicon, FPGA, and silicon environments.

• Balancing area, power, timing, schedule, and risk tradeoffs.

• Communicating technical issues across disciplines, including analog, layout, test, applications, and management.

• Managing several projects or blocks at once under tape-out deadlines.

• A mentoring mindset and commitment to raising team capability.

• Ability to exercise independence, ownership, and accountability over design contributions

• Drive to keep improving methodology, reuse, and automation.

• Attention to detail combined with a pragmatic, schedule-aware approach.

• Comfortable in a smaller team where larger impacts are required